26 years ago
Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D
This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET is one of the most attractive alternative to
26 years ago
Non-Stationary Transport Effects: Impact on Performances of Realistic 50nm MOSFET Technology
We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyzes, are applied to existing devices. This work shows
26 years ago
ATLAS can be used to perform large signal sinusoidal analysis
The Atlas syntax is flexible enough to allow the definition of sinusoidal nodal voltages by defining them on the SOLVE statement line. To illustrate this the structure shown in Figure
26 years ago
RF CMOS Modeling Using UTMOST III AC (S-Parameter) Module
This article presents a high frequency SPICE model parameter extraction method for CMOS devices. Current compact MOS models are developed for low frequency applications and provide good fits for DC,
26 years ago
New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT
New improvements have been added to Shur a-Si:H and Poly-Si Thin Film Transistors models. These enhancements include self-heating effect and a new charge conservation model.
26 years ago
BSIM4_U ( BSIM4 Universal Routine )
This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition.
26 years ago
Measure CJSWG (CJGATE) Capacitance using UTMOST III
For the UTMOST III versions greater than 17.2.0.R, the UTMOST users can measure the CJSWG (CJGATE) capacitance using the "CJ/CJSW" routine. The CJ/CJSW routine in MOS technology has been modified
26 years ago
Cross-Sectional Viewer in Expert
Cross-Sectional Viewer is a tool within Expert to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout. Cross-sectional Viewer is a link between the
26 years ago
Expert: Recent Improvements in Hierarchical Layout Inspection
The functionality of several features of Expert layout editor has been enhanced to deal with hierarchical layouts in more convenient ways.
26 years ago
Applicability of Distance Computation for Graphs to LVS Discrepancy Analysis
An important step in electronic circuit design is layout versus schematic verification (LVS)