Simulation Standard

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

24 years ago

Quantum Modeling Part I: Poisson-Schrodinger Solver

The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical effects, which are observed as shifts in threshold

24 years ago

Simulation of a High Gain InP/InGaAs/InP Double HBT with Varying Doping Profile within ATLAS

It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor materials. Typically a heterojunction bipolar transistor (HBT) consists

24 years ago

Order of Multiple Implants in a Process Affects Results

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will

24 years ago

Temperature Effects in SmartSpice LEVEL=6 Ferroelectric Capacitance Model From Ramtron

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of Silvaco Simulation Standard. This model utilizes a new

24 years ago

UFSOI V7.0 (UFPDB V2.0) Model Released in SmartSpice

Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to 21. SmartSpice uses version 7 by default, but

24 years ago

Managing SmartSpice / SmartView Simulation Output Raw Files

Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition is required prior to simulation. Constant disk access

24 years ago

Defining Voltage Controlled Oscillators in SmartSpice

One of the methods to define a Voltage Controlled Oscillator (VCO) in a SPICE simulation is to make use of a voltage-controlled voltage source (E element). A typical VCO expression

24 years ago

Geometry Binning for TFT models and SmartSpice Tips

Level=36 RPI poly-Si TFT and other original TFT models do not support automatic geometry binning. The enhanced model included with SmartSpice 1.9.7.C or later now supports the selecting of a

24 years ago

Advanced Features in Expert Layout Editing Tool: Parameterized Cells

Silvaco Expert is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase designer productivity by adding enormous flexibility and efficiency to

24 years ago

Expert Wiring Tool: Router at Hand

Modern complex circuit designs require automatic router functionality in circuit layout editors. In multi-layer hierarchical design, it is often necessary to build a single wire between two objects or arbitrary