The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d.

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?

Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The

With mounting concern for energy conservation and nature preservation, power electronics is becoming increasingly dominant in everyday life.

It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion

Mesh control in process simulators is one of the major issues tackled by any user. Over the years the meshing algorithms with SSuprem4 and ATHENA have been improved to the

Q: How can external tools be run inside of Silvaco's run-time environment DeckBuild? Is it possible to include UNIX commands along with simulator syntax inside an input file?

The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from a number of existing users.