GaN_Power_ex09.in : Vertical Superjunction GaN HEMT with P+ Gate and P-pillar

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GaN_Power_ex09.in : Vertical Superjunction GaN HEMT with P+ Gate and P-pillar

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Required Modules

Victory Device

2D Simulator

This example demonstrates TCAD computation of Id-Vg, Id-Vd, and Breakdown I-V characteristics of a gallium nitride (GaN) field-effect transistor (FET) called Enhancement-Mode Vertical Superjunction HEMT, with P+ Gate and P-pillar. The P+ gate region makes it a Normally-OFF (Enhancement-Mode) HEMT device.

The example is based on the following reference paper:

[1] L. Zhongda, T.P. Chow, “Design and simulation of 5-20-kV GaN enhancement-mode vertical superjunction HEMT “, IEEE Trans. Electron Dev, vol.60, no.10, 2013, pp.3230-3237.

This example demonstrates:

Construction of the Vertical GaN-FET structure using the device simulator syntax

Material and models parameter specification

Simulation of Id-Vg, Id-Vd, and Breakdown I-V characteristics

Display of the results

The device under consideration is a Normally-OFF Vertical Superjunction AlGaN/GaN HEMT. The main concept here is that the polarization charge is calculated using the built-in models as specified by the polarization parameter on the models statement.

First, the initial solution is obtained (for zero bias), which includes also calculation of the 2D Electron Gas (2DEG) sheet density.

Then, the Id-Vg transfer characteristic is computed, for one selected Vds voltage (corresponding to Fig. 9 in the reference [1]), and then the Id-Vd output characteristics are computed, for several selected Vgs voltages (corresponding to Fig. 8 in [1]). Finally, Breakdown I-V curves are computed.

Note that in the reference [1] a different device structure was used for the Id-Vg and Id-Vd analysis, and a different design (different dimensions and doping) for the Breakdown I-V. Therefore, the input deck has two separate sections:

– PART I: Id-Vg and Id-Vd curves computation

– PART II: Breakdown I-V curve simulation