23 years ago
HIPEX-Net: Hierarchical Layout Extractor for Expert Editor
HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted
23 years ago
“Shortest Path” Option for Flight Line Style (Net Bar)
There is the recent improvement in Expert Layout Editor, the “Shortest path” option was added to Flight line styles (Net Bar). This option allows to build the shortest tree (network)
23 years ago
Expert Layout Editor Recent Improvements: Over-the-Point Drawing of Orthogonal Shapes
This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers
23 years ago
Guardian DRC Edge Layer Operations
Recent versions of Guardian DRC introduce operations that involve edge layers, either on input or on output. An edge layer is a layer that contains line segments that are edges
23 years ago
Guardian LVS: New Platform-Independent GUI
We introduce a platform-independent version of Guardian LVS. An important feature of any tool is its capability to operate on various platforms and to support internationalization. Now Guardian LVS is
23 years ago
Counting Instances in an Expert Editor Layout
Q: I have some trouble counting the number of in-stances in a layout using Expert. I have tried to use the Chip Rover feature
23 years ago
Low Voltage Super Junction MOSFET Simulation and Experimentation
The application of Super Junction concepts to a low voltage power MOSFET is investigated. The body junction is modified with the addition of a high energy implant, resulting in an
23 years ago
Using The Statistical Sampling Feature in the BCA Monte Carlo Implant Simulator
Silvaco’s Binary Collision Approximation (BCA) Monte- Carlo Implantation simulator closely replicates the physics of implantation by individually tracking implanted ions and their resulting interstitial and vacancy damage as the ions
23 years ago
A Comparison Between Classical Full Chip Extraction and Field Solver Parasitic Extraction
This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC based on geometrical information, then using a field
23 years ago
ATLAS Simulation of an SEU Event in 2D
Q: Can ATLAS simulate an SEU event in 2D? To simulate a single event upset (SEU) is inherently a 3D problem because the alpha particle may strike the chip at