Models

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R The input deck shows how to use a G-device and a convex 3D-surface to generate current through the G-device. The input deck

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R This input deck shows you how to produce a single element noise source that can be used to probe circuit sensitivity and

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R This input deck shows you how to produce a single element Frequency Modulated Source waveform. Graphics Input Files Vsource_FM.in * Frequency Modulated

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 4.6.8.R This example shows how to use multiple Verilog-A modules in a simulation and to reference parameters of the module from the input

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.6.8.R This example shows how to implement a capacitor in Verilog-A and compares the waveform in a simple circuit transient simulation with a

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R A simple buffer with input/output signals is required. No example available at the moment. Input Files buffer_test.in Silvaco test deck for series_switch

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.REAC functionality here ! No example available at the moment. Input Files 6tr1cap_runtime.in 6TR1cap .OPTIONS DCGMIN=1E-18 .OPTIONS GMIN=1E-18 .options post=2 probe rawpts=800 nomod

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R GUI functionality to free up more memory by terminating programs etc. No example available at the moment. Input Files soa_bsim4.in * BSIM4

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 3.16.12.R No example available at the moment.

Requires: SmartSpice & Smartview Minimum Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Sencypt functionality for both individual lines and whole files. No example available at the moment.

Requires: SmartSpice & Smartview Minimum Versions: SmartSpice 4.18.16.R and SmartView 2.32.5.R This hierarchical design example demonstrates inverter-equivalent implementation of complex gates connected as a 4-Bit Carry Look Ahead (CLA) Adder