Casey Molver

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster. 

28 years ago

A common request from TCAD (Technology Computer Aided Design) users is advise on how to calibrate the process flow and device simulator to a particular technology. In this article, guidelines

28 years ago

FastBlaze uses novel device simulation techniques to simulate typical MESFET and HEMT characteristics in less than a minute. To be a truly useful engineering tool this extremely high speed must

CLEVER can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of CLEVER results with measurements made by SGS-Thomson Microelectronics were

28 years ago

The HP4155/56 DC Analyzer can be configured with SMU and Pulse Generator expander box frame called HP41501A. The expander box can have different measurement unit options.

28 years ago

An important aspect of statistical process control in IC production is the ability to predict circuit performance variation in the manufacturing process. Two new features in SPAYN allow the user,

28 years ago

The debut of Silvaco's new schematic editor, Scholar, is drawing closer. Scholar is a sophisticated design tool which derives its power and flexibility from the fact that it is built

28 years ago

In collaboration with STMicroelectronics Central R&D at Crolles (France), a new routine has been developed in UTMOST III to provide a complete solution for MOS Philips Model 9 parameter extraction.

28 years ago

The .ALTER statement is designed to allow a SPICE input deck to be re-run with a change in a single parameter. This feature is especially useful in characterization. For this

28 years ago

I run DRC, find one-two violations, correct them, then I re-run DRC to check whether my corrections worked. However re-running on the whole design is time-consuming. How can I run

28 years ago

Rectangular partitionings form a mathematical base for many modern approaches to automation of VLSI design [1-3]. In particular, popular methodologies of hierarchical placement (by cell grouping / merging) as well

28 years ago

In this paper we introduce one of the latest and most advanced features of Silvaco's Expert Layout processor for Windows NT ­ DRC Guard. DRC Guard is fully functional real-time

28 years ago

When using the analytical implant tables in ATHENA the default model for the lateral implant range assumes a gaussian profile with a standard deviation equal to the vertical standard deviation