Concluded event

SURGE Virtual Event North America 2025

North America · Wednesday, January 15, 2025 · Virtual event

At a glance

January 15, 2025

Date

North America

Region

Virtual

Format

20

Sessions in 3 tracks

About this event

On January 15, 2025, SURGE North America 2025 put 20 talks online in a single day.

SURGE exists so the engineers who use Silvaco tools can compare notes, with each other and with Silvaco. This edition gave the floor to Ciena, Silicon Creations and SilTerra, and to researchers from Stanford and TU Wien. Silvaco’s engineers covered the rest, from the CEO keynote down to a 3nm LDO.

Date

Agenda

Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.

General Session

Keynote

Babak Taheri, Chief Executive Officer and Director, Silvaco

Silvaco’s CEO and a board member since August 2019, apart from a break in late 2021. He joined as CTO and EVP of Products in October 2018, after VP and GM roles at Freescale (now NXP) and Cypress Semiconductor. He also chairs the advisory board of UC Davis’s Electrical Engineering department.

AI Takes EDA to the Next Level

Wally Rhines, President and CEO of Cornami and Silvaco Board Member

He ran Mentor Graphics as CEO from 1993 to 2017, then led Siemens EDA after the acquisition. He has run fabless chip company Cornami since March 2020 and joined Silvaco’s board in September 2022.

Semiconductor Process and Device Track (TCAD)

TCAD Update

Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco

Dr. Guichard brings you up to date on the Victory simulation tools, makes the case for TCAD in bringing up new devices, and sets out the TCAD roadmap.
He has led Silvaco’s TCAD division since November 2012. He started in 1995 at Silvaco’s French subsidiary, where his roles included applications engineer. PhD in semiconductor physics from Grenoble INP.

Products: TCAD

NanoHub Workforce Development

Dr. Peter Griffin, Stanford University

Co-author, with Jim Plummer, of the textbook Integrated Circuit Fabrication – Science and Technology (Cambridge University Press, 2024). He teaches semiconductor technology at Stanford and has spent two decades at the Stanford Genome Technology Center, much of it on digital microfluidics.

Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation

Sanam Moslemi-Tabrizi, Analog Engineer, Ciena

Ciena’s analog designers work from supplied models, and as geometries shrink, those models drift from reality: quantum effects take hold that classical simulators miss. So the team began building its own. Victory Atomistic handled the first requirements, since it solves Poisson and Schrödinger self-consistently, and joint work with Silvaco extended it from there. Fabrication detail on Ciena’s 5nm devices was limited, yet the simulated trends follow room-temperature lab data well, if not point for point. The next target is qubit work, using simulation in place of costly cryogenic measurements. The solver still needs work to converge reliably at the coldest temperatures and lowest bias.
She verifies analog circuits at Ciena and develops its quantum device models. Earlier, as a Research Associate at Carleton University, she built a full-vectorial mode solver that went into a LiDAR beam-scanning design.

Products: Victory Atomistic

Machine Learning for Multi-Scale Plasma Process Integration and Optimization

Associate Professor Dr. Lado Filipovic, TU Wien

Etch simulation for TCAD has a scale problem: what happens across the plasma chamber and what happens inside one high-aspect-ratio feature have to be solved together. Dr. Filipovic’s group links the two with machine learning and with feature-scale models informed by the equipment. Its surrogate models, trained on runs of the Hybrid Plasma Equipment Model (HPEM) plus experimental data, predict fluxes quickly. That speed opens the way to a digital twin and, in time, real-time optimization. The goal for the fab: less trial and error, and a greener process.
He directs the Silvaco-supported Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at TU Wien’s Institute for Microelectronics. His group released the open-source process simulator ViennaPS, and he serves on the IEDM and SISPAD technical program committees.

Products: Victory Analytics · Victory DoE

How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data

Dr. Stefania Carapezzi, Field Applications Engineer, Silvaco

Matching TCAD parameters to measured data has mostly meant an expert working by trial and error, and that pace doesn’t fit a shrinking time-to-market. This session hands the job to machine learning, using two Victory tools in one flow. Victory DoE runs the design of experiments across your TCAD simulations and collects the outputs. Victory Analytics then fits the TCAD parameters to your experimental data. The worked case is an AlGaN/GaN HEMT.
Field Applications Engineer at Silvaco France since March 2023. Her PhD in physics is from the University of Bologna, and her research used TCAD to simulate beyond-CMOS devices and the quantum effects inside very small transistors.

Products: Victory Analytics · Victory DoE

Applying Artificial Intelligence in Fab Technology Co-Optimization

Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco

Process and fab engineers normally tune a fabrication step with wafer-based Design of Experiments. When one parameter keeps missing its target, that loop can stretch across weeks or months. The alternative is a simplified but accurate machine learning model of the step, and that approach is already in production use. Silvaco’s FTCO platform builds the model from your fab data and TCAD data, as a semiconductor digital twin. Worked examples show the FTCO flow end to end, so you can judge where it fits your team.

He joined Silvaco in Boise in June 2023. Before that he spent 13 years at Micron, where he led the 3D NAND cell team and worked on the emerging-memory program with imec. His PhD in microelectronics is from Grenoble INP.

 

Products: FTCO

Utilizing Physics-Based AI-Powered Digital Twins to Accelerate Design Optimization and Manufacturing Yield of SiC Power Devices

Dr. David Green, TCAD Applications Engineer, Silvaco

Based in Cambridge, UK, he has spent 18 years at Silvaco supporting TCAD customers across EMEA on power, display, reliability and optical work, and managing TCAD R&D projects. His PhD covered vertical and lateral power devices.

Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology

Dr. Bogdan Tudor, Head of Modeling, Silvaco

Three device technologies, Si, GaN and SiC, and three ways to model them for SPICE: compact models, macromodels and Verilog-A. The bulk of the talk is one worked case, a SiC DMOS. Its extraction starts from I-V and C-V curves and the bias-dependent capacitances. From there the model is tuned on dynamic characteristics, and dynamic temperature effects go in last.
He heads Silvaco’s Device Characterization Group, covering its modeling services, field operations and R&D, and joined Silvaco in 2017. Before that he spent four years at ProPlus Design Solutions and twelve at Synopsys.

Products: FTCO

IC Design Track (EDA and IP)

EDA and IP Updates

Ben Louie, VP and GM of IP Business Unit, Silvaco

Ben Louie reports on the Analog and Custom IC portfolio: which features and functions are new, and the plan for Silvaco’s EDA tools after them.
He leads Silvaco’s semiconductor design IP, with more than 22 years in NOR flash, NAND flash and MRAM design. At Micron he led the design team through the move from NOR to NAND and ran design on its first NAND products. He holds 123 US patents. t email.

Products: Analog and Custom IC

EDA Solutions for Physical Design of Discrete Power Devices

Stefano Pettazzi, Staff Applications Engineer, Silvaco

Power device layouts often carry many curved shapes, and curved geometry is hard for DRC engines to check. Stefano Pettazzi draws such a layout in Expert, then runs SmartDRC on it at speed with its accuracy intact. He ends on the joint TCAD and EDA flow Silvaco offers for power devices, so one supplier covers both halves.
A Silvaco applications engineer since 2012, he supports customers’ EDA flows from front-end design through back-end layout, with nearly 25 years in EDA and microelectronics behind him. M.S. from the University of Pavia.

Products: Expert · SmartDRC/LVS

Accelerating the Verification of High-Frequency Analog Mixed-Signal Components via Jivaro Pro Advanced Parasitic Reduction

Chung-Chun Chen, Director of Analog Design, Silicon Creations

He leads the SerDes team at Silicon Creations in Atlanta, where he has worked since 2011, apart from 2018 to 2019 at Realtek’s Ubilinx Technology. He holds a PhD from National Taiwan University and is an IEEE Senior Member.

Products: Jivaro Pro

Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues

Carlos Berlitz, Corporate Applications Engineer, Silvaco

Where exactly is the parasitic problem in an advanced-node block? Simulation will tell you, eventually. Viso goes straight to the extracted RC network instead, with timing estimates, crosstalk and net-to-net matching, and points you to the nets that need attention. The demo uses high-speed circuits and skips the long simulation loops.
He has supported Silvaco’s RC parasitic analysis and reduction tools since 2023 and contributes to their roadmap. PhD from INSA Lyon.

Products: Viso

Standard Cells Characterization Challenges and Improvement

Siti Mariyam, IP Design Enablement, SilTerra

Foundry processes don’t stand still at SilTerra, and each enhancement sends its IP libraries back through optimization and validation. Siti Mariyam explains how Silvaco tools fit that loop in SilTerra’s library development, and the characterization time they save.
She develops and validates standard cell and IO libraries at SilTerra Malaysia. Degree in electronics system engineering from Universiti Teknologi Malaysia.

Products: Standard Cell

Standard Cell Library IP in Advanced FinFET Nodes for Low Voltage Applications

Fernando Carrion, Design Engineer, Silvaco

Run standard cells at low voltage on an advanced FinFET node and the key metrics move: area, timing, power, variability. Fernando Carrion works through why, then introduces Silvaco’s low-voltage FinFET libraries. Inside: a Power Management Kit (PMK), high fan-in cells whose transistor stacks are kept short, and flip-flops in multi-bit and retention versions. With multi-threshold options, you pick the trade between speed and power.
A Silvaco design engineer with more than four years spent designing and characterizing standard cells. He graduated from UFRGS and is certified as an analog circuit designer through the IC Brazil program.

Products: Cello FinFET

Advanced Node Library Development with Cello FinFET

Felipe Bortolon, Engineering Manager IP, Silvaco

Porting a standard cell library to a new advanced node is slow by hand. Felipe Bortolon demonstrates Cello FinFET reusing an existing library for that move, and producing GDSII straight from CDL.
He manages engineering for Cello, Silvaco’s standard cell layout automation framework. MSc in microelectronics from UFRGS.

Products: Cello FinFET

Bandgap References for Low Voltage Operation

Ahmad S. Mazumder, Director of Engineering, Silvaco

Two bandgap voltage references, designed by Silvaco on TSMC’s N3P process (3nm FinFET), at 0.45 V and 0.92 V. Across -45°C to 150°C, each holds within 1%. That is the whole point of a reference circuit: an output that shrugs off process, temperature, supply and load, over time.
Director of Engineering in Silvaco’s IP Division since 2019, responsible for developing and supporting its analog and interface IP. He spent 28 years before that on DDR, high-speed SerDes, interfaces and ESD at Intel, Broadcom and C-Cube Microsystems.

LDO For Low Voltage Operation

Shaikh A Shams, Staff Engineer, Silvaco

A capless LDO designed in TSMC’s N3P 3nm FinFET process. The key figures:

  • Load current: up to 30 mA
  • Input: 1.2 V ±10%
  • Output: programmable, 0.45–0.9 V in 50 mV steps
  • PSRR: >40 dB at 1 kHz, >29 dB at 10 MHz, across all PVT corners (-40°C to 125°C)
  • Load transient: <18 mV undershoot or overshoot for a 1 A/ns step, across the same corners
  • Area: <3,400 µm²
Staff Engineer in Silvaco’s Analog/Interface IP Division since 2020, after 22 years on SerDes, interfaces, voltage regulators and AMS design at Intel, GlobalFoundries and Dialog Semiconductor. MS from the University of Arizona.

Introduction to CAN-XL

Mauricio Brochi, Director of Automotive IP, Silvaco

Classic CAN, from 1986, settles bus contention by non-destructive arbitration: the higher-priority frame wins, and a faulty node is cut off while everyone else keeps talking. By 2011, ECU data packages had outgrown it, and CAN FD lifted the limits to 8 Mbps, with payloads of 64 bytes. CAN XL, the third generation, reaches 20 Mbps and 2,048-byte payloads. It also bridges to 10BASE-T1 and other Ethernet standards, as vehicle networks take on software-defined designs.
More than 30 years in SoC systems and IP for automotive and industrial applications, including CAN controllers, microcontroller cores and cryptographic accelerators at Motorola and NXP. Degree in electronic engineering from the University of Campinas.

Products: Automotive IP

Themes at SURGE North America 2025

From SiC digital twins to DRC on curved discrete-device layouts

Victory Atomistic for quantum transport, machine learning for plasma etch, and the TCAD update

SilTerra on characterization, then two Silvaco talks on FinFET libraries

The FTCO flow, plus TCAD calibration with Victory Analytics and Victory DoE

Expert and SmartDRC on power layouts, Jivaro Pro and Viso on parasitics

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Events

Upcoming shows, with booth numbers where Silvaco has one

Webinars

Recorded sessions on plasma chamber simulation and I-V prediction from process geometry