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Mixel D-PHY RX+: D-PHY receiver with full-speed loopback test D-PHY RX+ is a MIPI D-PHY receiver that carries its own simplified transmitters, so your SoC’s camera or display input can

Mixel D-PHY TX+: D-PHY transmitter with full-speed loopback test D-PHY TX+ pairs Mixel’s MIPI D-PHY transmitter with a receiver of its own, so when your SoC drives the camera or

LVDS Deserializer IP An LVDS deserializer from Mixel, a Silvaco company, for the SoC that sits at the far end of the link and needs its four serial channels back

LVDS serializer IP LVDS serializer IP from Mixel, a Silvaco company, for teams whose SoC sends parallel data to a display panel over four LVDS channels, available at TSMC 40LP

Multi-standard SerDes IP: 1.0 to 4.25 Gbps Four channels of silicon-proven multi-standard SerDes IP from Mixel, a Silvaco company, for SoC teams running PCI Express, SATA, XAUI or backplane links

D-PHY LVDS combo receiver IP Mixel’s D-PHY LVDS combo receiver IP gives your SoC a single input PHY that takes MIPI D-PHY over four lanes or LVDS over four channels,

D-PHY and LVDS combo transmitter IP A D-PHY LVDS combo transmitter from Mixel, a Silvaco company, for the sending end of a display or camera link: one PHY drives a

MIPI C-PHY and D-PHY combo IP: one interface, both standards Silvaco’s C-PHY/D-PHY combo IP is one PHY for either standard, built for SoC architects who don’t want to lock a

Other IP: IEEE 1149.7 TAP controller for debug and test Short on pins? Silvaco’s IEEE 1149.7 TAP controller runs your SoC’s test and debug over two of them. It connects

Power management IP: LDO regulators and voltage references Silvaco power management IP gives your TSMC 3 nm N3P design two LDO regulators and a bandgap reference, so every block on

Embedded processor IP: ColdFire and 8051 cores Put a 32-bit ColdFire core or an 8-bit 8051-compatible core into your SoC. Silvaco licenses this embedded processor IP as synthesizable Verilog, either

MIPI M-PHY IP: high-speed serial physical layer If your SoC needs UFS flash storage or a chip-to-chip link, Silvaco’s MIPI M-PHY IP gives you an M-PHY v4.1 physical layer running