Daily Archives: May 1, 2004
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May 1, 2004
Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.
22 years ago
STELLAR – Process Based Parasitics Capacitance Extraction on Large Custom Cells
SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design.
22 years ago
LPE Optimization with Clever/Hipex/Exact Linkage Methodology
On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower.
22 years ago
When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers
When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a real problem. Previous methods suggested in the hints