May 1, 2004

SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design.

On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower.

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a real problem. Previous methods suggested in the hints