Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice

A new notation has been introduced into SmartSpice to allow a compact expression of a multiple bit wire buss to be used. From this expression the user can simply state

Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design

HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance extraction tool.

SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco’s Maverick, which is a part of Guardian LVS/ERC. While being fully compliant with Maverick, HIPEX-NET

In previous versions of Guardian DRC there were only two ways of measuring the distance between two segments: the ordinary, Euclidean metric, and the square metric, which behaves differently when

Q: I would like to highlight two nodes at the same time in Expert. I currently use Verification->Node Probing->Pick Node to highlight a node, but I donít see how I

Spreading Resistance Profiling (SRP) retains its popularity in the semiconductor industry by an inexpensive means of capturing dopant profile information. However, device engineers often incorporate SRP data into process simulation

An eye diagram is a convenient way to visualise how the waveforms used to send multiple bits of data can potentially lead to errors in the interpretation of those bits.

An effective device structure for reducing leakage current in BH laser diodes with semiin-sulation doped Fe in InP blocking layers has been analyzed [3]. In this study, the leakage current