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2003

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

23 years ago

Sometimes I have problem to skip cells when importing cells

Q: Sometimes I have problem to skip cells when importing cells with the same names from reference library. Once we skip one cell, expert will complain other cells already exist

23 years ago

Guardian DRC vs. Other DRC Systems, I

1. Introduction This article begins a series of articles that describe the compatibility of Guardian DRC system[1] in terms of functionality: command set, syntax and implementation with other leading industrial

23 years ago

Schematic Driven Layout

Expert schematic driven layout (SDL) is a CAD tool which increases the productivity of layout design by automating cell generation and providing visual cues to assist the wiring process. In

23 years ago

Interactive P-cell Generation

1. Abstract Parameterized cells (P-cells) significantly increase the productivity of layout designers. Silvaco International’s tool Expert has been designed to aid layout designers through its ability to support and manipulate

23 years ago

Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release

Introduction This article introduces the new features and numerical schema implemented in the most recent release of Clever from Silvaco. In this new release, both memory handling and simulation time

23 years ago

Is there a way to automatically specify mesh spacing in ATHENA?

Q. Is there a way to automatically specify mesh spacing in ATHENA? A. Yes, there are three ways to automatically specify grid spacing. The most preferred method is described below

23 years ago

Topography Simulation of Trench Etch Using Monte Carlo Plasma Etch Model with Polymer Re-deposition

1. Introduction The topography simulation module, Elite has constantly been improved in order to simulate advanced processes, which are becoming more complex with device miniaturization and further integration of VLSI

23 years ago

TCAD Simulation of a Polysilicon Thin Film Transistor For Active Matrix Liquid Crystal Displays

Polysilicon thin film transistors are attractive as active devices in driver circuits of highly integrated active-matrix liquid crystal displays (AMLCDs) and as p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) in static

23 years ago

IBIS Models in SmartSpice

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which

23 years ago

New Features in SmartSpice 2.3.4.C

A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the