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2002

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

24 years ago

The Valdinoci Temperature Dependent Impact Ionization Model for Silicon

Impact ionization plays an important role in the design of many semiconductor devices. Since impact ionization is both temperature and electric field dependent, it is important to use a model

24 years ago

Reproducing Basic Experiments in ATLAS to Study the Transient Decay of Carriers

ATLAS may be used to study these effects. A standard experiment for studying recombination in silicon is the transient decay of photoexcited carriers - known as the Stephenson-Keyes method for

24 years ago

BSIM3SOI Version 3.0 Model Released in SmartSpice

BSIM3SOI version 3.0 model was released on May 2002 by UC Berkeley. This model includes both Partially and Fully depleted models. This model is now implemented in SmartSpice and can

24 years ago

A New Surface-Potentials Based MOSFET Model: HiSIM

HiSIM is based on a charge-sheet model. IDS current is described using only one equation, and there-fore is continuous over the whole range of operating regions. This improves MOSFETs modeling

24 years ago

HiSIM Version 1.0 Model Released in UTMOST III

HiSIM is a MOSFET model for SPICE circuit simulation that has been developed by Hiroshima University and STARC Company. This model present several advantage on the extraction point of view,

24 years ago

Measure Low Current FT in Bipolar devices

The input impedence of most network analyzers are around 1 MOhm, which is relatively small. Due to this low impedence the leakage current on the Base port (Typically Port1) becames

24 years ago

Parallel DRC by Functional Decomposition of DRC Decks

A new version of Savage DRC system taps the full power of multiprocessor computers by introducing simultaneous execution of DRC commands from a DRC deck. A DRC deck is a

24 years ago

Expert Layout Editor, Savage DRC System and Guardian LVS for Linux Platform

Silvaco Data Systems announces the release of CELEBRITY CAD suite: Expert layout editor, Savage DRC system and Guardian LVS for Linux platform.

24 years ago

Modification of BEM for Precise Capacitance Extraction

It is well-known that parasitic effects are no longer negligible for modern integrated circuit technology. Among the most important parasitic effects limiting the chip performance are interconnect related problems like

24 years ago

Advanced Layout Editing Using XI-scripts

To provide uniform etching of metal, dummy metal rectangles can be placed over an unused area of the chip. The following script generates dummy layer with a full array of