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3 weeks ago

013_bsim4_cap_table : BSIM4 device capacitance table

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R The input deck is a single BSIM4 device ……. Graphics Input Files bsim4.va /*****************************************************************/ /* Berkeley BSIM4.3.0 Verilog-A model */ /*****************************************************************/ //

3 weeks ago

014_verilog-a_inverter : Inverter using Verilog-A module

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R The 2 bit MOSFET adder input deck with .TRAN and .MEASURE analysis shows by rubberbanding the voltage source pulse parameters the sensitivity

3 weeks ago

015_dot_net : NET analysis variations

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R A simple .NET analysis is performed in input deck and rubberbanding c[cap] you can see the output response sensitivity to changes in

3 weeks ago

016_fft_sim : FFt variations

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R A simple input deck running .FFT and .MEASURE analysis on a circuit shows variation in response to changes in the frequency of

3 weeks ago

017_jitter_noise : Noise Jitter influences

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R A simple 9 Stage inverting Ring Oscillator is used with an external N element noise source injected through a capacitor to show

3 weeks ago

018_noise_plot_measure : Noise plot variations

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R The input deck uses both .NOISE and .MEASURE analysis to show influences on AC noise levels. Input Files rubberband_example_18.in *** * The

3 weeks ago

019_5th_order_lp_filter : 5th order LP Filter variations

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 4.6.5.R The circuit input deck is a 5th-order Lowpass filter containing pole zero analysis (.PZ). Rubberband r*[res], c*[cap] and l*ind] parameters to see

3 weeks ago

001_mos_op : MOS OP point

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R In this input deck a simple MOS level=3 device is optimized against a DATA set for a DC family of curves and

3 weeks ago

002_dc_op : Modulated sources as single element in circuit.

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R This input deck shows you how to produce a single element Frequency Modulated Source . Input Files mod1.in Parametric analysis ***** Circuit

3 weeks ago

003_ac_op : Verilog-A

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin inp 0 PULSE(0 3 0

3 weeks ago

004_tran_op : IBIS Buffer

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R Example 4 illustrates The input deck file ….. Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin

3 weeks ago

005_buffer_delay : Buffer delay/risetime optimized for Vdd

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck contains a buffer circuit to be optimized for geometry (W/L) to get the best rise, fall and delay times