Optimizer

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Optimizer

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

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1 week ago

001_mos_op : MOS OP point

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R In this input deck a simple MOS level=3 device is optimized against a DATA set for a DC family of curves and

1 week ago

002_dc_op : Modulated sources as single element in circuit.

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R This input deck shows you how to produce a single element Frequency Modulated Source . Input Files mod1.in Parametric analysis ***** Circuit

1 week ago

003_ac_op : Verilog-A

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin inp 0 PULSE(0 3 0

1 week ago

004_tran_op : IBIS Buffer

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R Example 4 illustrates The input deck file ….. Input Files mod1.in Parametric analysis ***** Circuit description vcc vss 0 DC vccDC vin

1 week ago

005_buffer_delay : Buffer delay/risetime optimized for Vdd

Requires: SmartSpice & Smartview Minimum Versions: SMARTSPICE 3.16.12.R The input deck contains a buffer circuit to be optimized for geometry (W/L) to get the best rise, fall and delay times