Testability
IP testability: full-speed internal loopback for PHY IP
Mixel D-PHY transmitters and receivers, now part of Silvaco, that check their own link at full data rate inside your SoC, on the production floor and in the finished system.
Testing built into the PHY, not bolted on later
A link fault found late can cost you a re-spin. Without test in the PHY, checking the link at its real data rate falls to
a tester on the serial pins. Or to a Universal configuration, and the extra area it carries. The plus
configurations make IP testability part of the block you license.
D-PHY TX+
Your transmitter gets its own receiver for loopback, so it checks itself at full speed inside the chip. That adds roughly 10% area over a plain TX, yet it still comes in about 30% smaller than a Universal configuration, with 40% less leakage power. Built for CSI-2, DSI and DSI-2.
D-PHY RX+
A few simplified transmitters exercise your receiver’s data lanes at full speed, in place of a full Universal lane. The design is patented, and it needs about 35% less area and 50% less leakage power than Universal.
What the plus means
Every TX+ and RX+ part in the Silvaco catalog carries full-speed internal loopback. The loop runs at the link’s real data rate, kept apart from the load on the serial pins. You get full-speed testing in production and in-system, and an analog test bus as well.
When you need the link tested at speed
Production test of PHY interfaces, checking each die at full data rate in volume manufacturing.
Silicon bring-up and debug, using in-system diagnostics and the analog test bus.
Designs where an external tester can't reach the interface, such as safety-sensitive automotive and medical parts.
Production-ready on these processes
Mixel was the first to take D-PHY to real silicon, with MIPI PHY work going back to 1998. Here’s where the catalog’s plus parts sit today, by foundry and node.
TSMC: N5, N6, 16FFC, 22ULL, 28HPC+, 40ULP, 65LP, 90LP
Samsung: 28FDSOI
GlobalFoundries: 22FDX+
ST: 28FDSOI, 40LP
UMC: 40ULP
~30% · ~40%
less area and leakage power for the D-PHY TX+, set against Universal
~35% · ~50%
the same comparison for the patented D-PHY RX+
100%
test coverage: the whole RX+, and the TX+ hard macro blocks
U.S. Patent 10,289,511
granted for the D-PHY RX+ implementation
Customer · Mixel MIPI IP (D-PHY parts)
November 2025
indie
indie builds automotive radar processors and MMICs, and chose Mixel as its MIPI IP provider. The parts it licensed were ASIL-B MIPI D-PHY CSI-2 transmitter and receiver IP, with functional safety deliverables and a safety manual.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
Summer 2026
PRO IP product selection guide
All the plus parts, listed by foundry, process node and part number.
Press release
March 2026
Mixel MIPI PHY IP now available as PRO IP
Includes the patented D-PHY RX+, announced in 2015 and now running in mission-critical production designs.
Find out if your node is covered
Tell an IP specialist which MIPI standard, foundry and process node you’re designing for.
You’ll hear whether a plus part already exists there, and how licensing works. Or book a
technical briefing on D-PHY testability.
IP testability questions
What is IP testability?
IP testability is test circuitry designed into the IP itself, so a chip can check its own interface in manufacturing test and after it ships. Mixel's MIPI PHY IP carries embedded DFT features, loopback BIST among them. On the TX+ and RX+, that extends to at-speed testing in production and in the field, plus an analog test bus.
What does the plus suffix mean on a Mixel part?
The plus marks Mixel's proprietary test configurations, TX+ and RX+, and each one comes with full-speed internal loopback testability. A Universal configuration can loop back at full speed as well. The difference is area: Universal carries circuitry for every lane use case, and the plus parts leave it out.
What is full-speed internal loopback?
The PHY routes its own high-speed signal back to itself on-chip, which checks the link at the rate it will run in the product. A TX+ closes the loop with a built-in receiver, and an RX+ with a few simplified transmitters. Either way, loading on the serial pins doesn't reach the test.
Which parts include testability?
The Silvaco catalog lists seven D-PHY TX+ parts and one D-PHY RX+, and the C-PHY/D-PHY combo adds eight TX+ and three RX+. MIPI C-PHY, the LVDS/D-PHY combo and LVDS carry one TX+ each. Universal D-PHY and combo parts support full-speed loopback too.
Does testability cost area or power?
Less than the alternative does. Compared with a Universal configuration, a D-PHY TX+ cuts area by roughly 30% and leakage power by roughly 40%, while adding only about 10% over a plain transmitter. The patented D-PHY RX+ saves more still: over a third of the area and about half the leakage.
Is testability available on every standard?
No. You'll find plus parts for MIPI D-PHY, MIPI C-PHY, LVDS and both combos, though on C-PHY, LVDS and the LVDS/D-PHY combo they're transmitters only. MIPI M-PHY, the LVDS deserializer and the LVDS/D-PHY combo receiver have no plus part in the catalog, so ask an IP specialist about yours.
Related IP
D-PHY TX+
The transmitter that loops back through its own receiver
D-PHY RX+
The patented receiver, tested at full speed
MIPI D-PHY
Transmitters, receivers and Universal parts by foundry and node
Multi-Standard
C-PHY/D-PHY and LVDS/D-PHY combos, with most of the remaining plus parts
Design IP
The full IP portfolio, family by family