Multi-Standard
Multi-Standard SerDes IP: Combo and Configurable PHY
Multi-standard SerDes IP from Mixel, a Silvaco company, for when your SoC has to speak more than one interface standard.
Multi-standard SerDes IP, by combination
Start from what sits on the other end of your link.
C-PHY/D-PHY Combo
Your camera or panel may be C-PHY or D-PHY. One PHY runs either mode, as TX, RX, TX+, RX+ or Universal, at up to 8.0 Gsps per trio or 6.5 Gbps per lane. You’ll find it at TSMC, N2P through 65 nm, and at ST in 28FDSOI and 40LP.
D-PHY/LVDS Combo TX
When your transmit side has to reach MIPI and LVDS receivers, this pairs a D-PHY transmitter with a four-channel LVDS serializer, TIA/EIA-644 compatible. Two parts: a DSI TX+ in GlobalFoundries 22FDX+ (4 channels, 4 lanes; LVDS to 1039.5 Mbps, D-PHY to 2.5 Gbps) and a CSI-2 TX in Tower 65BSB.
D-PHY/LVDS Combo RX
Taking video in from both MIPI and LVDS sources? This one PHY receives either, with D-PHY lanes and TIA/EIA-644 LVDS channels. It ships as a CSI-2 RX in TSMC 28HPC+ with four channels and four lanes, at 600 Mbps LVDS and 1.5 Gbps D-PHY.
4.25 Gbps SerDes
Not every multi-standard link is MIPI. This quad SerDes gives you four channels, each running 1.0 to 4.25 Gbps, for PCI Express, SATA, RapidIO, XAUI, Fibre Channel or backplane links. It’s silicon proven, with no part in the catalog, so your foundry and node come first in the conversation.
Where one PHY beats two
Designs that must support two standards on one interface
Set one PHY to either standard, and drop the second PHY from the floorplan.
Camera and display links with mixed sources
Mix C-PHY and D-PHY cameras or displays on one link, with CSI-2 and DSI available whichever mode it runs.
The combos are in silicon at four foundries
Across all its MIPI PHYs, Mixel has working silicon at nine foundries and twelve nodes. Start with yours.
N2P to 65 nm
C-PHY/D-PHY combo parts at TSMC, plus ST 28FDSOI and 40LP
3 foundries
for the D-PHY/LVDS combos: GlobalFoundries, TSMC and Tower
8.0 Gsps · 6.5 Gbps
per trio and per lane, from the Universal configuration in TSMC 16FFC
2016
the year Mixel became the first IP provider with silicon-proven MIPI C-PHY, on this combo
Industry · C-PHY/D-PHY Combo
May 2026
MIPI Alliance
Said of the C-PHY/D-PHY Combo Universal on TSMC N2P, which adds D-PHY v3.6 embedded clock mode and moves the same throughput over 25% fewer wires.
“Mixel, now part of Silvaco, has long been a valued contributing member of the MIPI Alliance. It is great to see these two companies combining their strengths to deliver MIPI C-PHY and D-PHY solutions on TSMC’s advanced N2P process.”
Hezi Saar, chair of MIPI Alliance
Customer · MIPI D-PHY
November 2025
indie
indie's automotive radar processors and MMICs integrate Mixel's ASIL-B D-PHY CSI-2 transmitter and receiver IP.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability.”
Peter Gulden, EVP Radar Systems and Software at indie
Catalog · PDF
Summer 2026
PRO IP product selection guide
Every C-PHY/D-PHY and D-PHY/LVDS combo part with its foundry, node and part number, alongside the rest of PRO IP.
Press release
March 2026
Mixel MIPI PHY IP now available as PRO IP
Both dual-mode combos are in it: C-PHY v2.1 with D-PHY v3.5, and D-PHY with TIA/EIA-644 LVDS.
Technical detail · mixel.com
March 2026
Mixel multi-standard SerDes
Full specifications for all four products, on Mixel's own pages.
Bring your two standards and your node
Which two standards, on which process? Start there, and an IP specialist covers licensing, deliverables and foundry availability for our multi-standard SerDes IP. Your license includes the first year of support.
Multi-standard SerDes IP questions
What is a multi-standard SerDes?
It's a single physical layer built to carry more than one interface standard, so one block covers links that would otherwise need two. Mixel, a Silvaco company, makes three types: C-PHY or D-PHY in one combo, D-PHY paired with LVDS, and a quad SerDes that handles PCI Express, SATA, XAUI and other serial links.
When is a combo PHY better than two separate PHYs?
When one interface has to accept either standard, such as a camera or panel that could be C-PHY or D-PHY. The combo configures a single PHY for whichever mode the link needs, and its C-PHY mode reuses the D-PHY circuitry and pins instead of adding a second set. Ask an IP specialist to cost it against two PHYs.
Which combinations are available?
Four: C-PHY/D-PHY, a D-PHY/LVDS transmitter, a D-PHY/LVDS receiver, and Mixel's 4.25 Gbps quad SerDes. The first three have production-ready parts in the PRO IP catalog. The SerDes has working silicon but no catalog listing; an IP specialist confirms foundry and node case by case.
Does a combo part cost area?
Some, though Mixel keeps the overhead small. The C-PHY/D-PHY combo builds its C-PHY mode from the same blocks and pins as its D-PHY mode, and its Universal, TX+ and RX+ versions add full-speed loopback test for very little extra area. Mixel doesn't publish an area figure; request one for your node.
Which foundries and nodes?
C-PHY/D-PHY combo parts cover TSMC N2P through 65 nm, N5, N6, N7 and 16FFC among them, plus ST 28FDSOI and 40LP. For D-PHY/LVDS, the parts sit at GlobalFoundries (22FDX+), Tower (65BSB) and TSMC (28HPC+). The quad SerDes has no catalog part.
What is the maximum data rate?
That varies by product. In C-PHY mode the C-PHY/D-PHY combo runs 8.0 Gsps per trio, roughly 18.24 Gbps, and in D-PHY mode 6.5 Gbps per lane. D-PHY/LVDS parts top out at 1039.5 Mbps on each LVDS channel and 2.5 Gbps on each D-PHY lane, and the quad SerDes at 4.25 Gbps per channel.
Related
C-PHY/D-PHY Combo
One PHY, either MIPI mode, at TSMC and ST.
D-PHY/LVDS Combo TX
Transmit to MIPI and LVDS receivers from a single PHY.
D-PHY/LVDS Combo RX
A D-PHY receiver with LVDS deserializers built in.
4.25 Gbps SerDes
Four SerDes channels at up to 4.25 Gbps each.
MIPI IP
The single-standard PHYs: D-PHY, C-PHY and M-PHY.
LVDS IP
LVDS serializers and deserializers on their own.