Casey Molver

Q. What is the typical method of measuring flicker noise using S3245A Noise Amplifier?

The importance of the MOS device SPICE model validation and the introduction of the validation routine in UTMOST III was presented in Simulation Standard article issued on September 1996. The

A new feature has recently been added to UTMOST: the ability to convert UTMOST log files into a format suitable for viewing in TonyPlot. This new feature is controlled from

In a previous article [1], the efficient use of the SmartSpice .MODIF statement for cell characterization was discussed. This article will focus on using advanced features of the SmartSpice scripting

Thin film transistors (TFTs) have an important application in the manufacture of active matrix LCD displays. As this technology has become more mature, a number of different models of both

The SmartSpice Interface to Cadence integrates the Analog Artist and Composer elements of the Cadence Design Framework II (DFII) with SmartSpice. This integration is accomplished, in versions 4.4.0 and later

Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a

The Berkeley BSIM3SOI model, released in December 1997, is now available within SmartSpice as the MOSFET level=25 model. This model incorporates three separate implementations: the original Berkeley model implementation is

The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete point set with a given distance threshold d.

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?