Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.
Required Modules
Victory Process
- 3D Diffusion & Implantation
- 3D Stress
Victory Mesh
- 3D Meshing
Victory Device
- 3D Simulator
For devices with a gate length of 28nm and below, it is possible to obtain significant mobile carrier mobility enhancement for most of the channel length, using remotely located epitaxial stressor material in the source drain regions. Using mobility enhancement techniques like this for p-channel devices can reduce the need for wider gate widths to match complimentary n-channel current drives, allowing the possibility of truly symmetrical layouts for complimentary MOS designs.
In this example, we show the effects of mobility enhancement using epitaxially grown SiGe source-drain regions in a 7nm p-channel FinFET. The stress calculation is invoked during the process simulation with the Stress exposed statement line. This calculates the stress induced by the SiGe epitaxial source-drain regions. At the end of the process simulation, any additional stress induced by subsequent processing steps is adjusted for by the Stress exposed rebalance line. The stress calculations are saved into the final structure file, which is then exported to Victory Device. The strain induced mobility enhancement is calculated in the mobility material=silicon model.iso=1 nhance phance line. These enhanced mobility values are then included into any subsequent mobility model.
The first device simulation calculates the un-saturate IdVg curve without invoking the strain enhancement calculations, whilst the second device simulation takes strain into account. The difference due to the strain enhanced mobility is shown in the final plot.
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