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Requires: CLEVER This example is based upon an EXNOR custom cell layout and illustrates how CLEVER may be used to extract the full parasitic netlist from a complete cell. Beginning

Requires: CLEVER This example is identical to example clex06.in except that the etching models have been upgraded to a more physical 87 degree side-wall. The same EXNOR custom cell layout

Requires: CLEVER An inverter is one of the most common cells found in layouts. This example contains one inverter cell designed with 4 NMOS and 4 PMOS transistors. It is

Requires: CLEVER An inverter is one of the most common cells found in layouts. This example contains one inverter cell designed with 4 NMOS and 4 PMOS transistors. It is

Requires: CLEVER An inverter is one of the most common cells found in layouts. This example contains one inverter cell designed with 4 NMOS and 4 PMOS transistors. It is

Requires: CLEVER Modern designs make use of mask layers which are not always at right angles to each other. The layout used in this example illustrates a 45 degree angle

Requires: CLEVER A useful option included within Clever is its ability to operate in 2D or 1D mode. This greatly reduces simulation time and allows the user to check that

Requires: CLEVER This example demonstrates the use of CLEVER to analyze non planerised structures such as local interconnects commonly used in current sources and in memory cells. To emphasise the

Requires: CLEVER This example demonstrates the ability of CLEVER to deposit and field solve non planarised, multi-layer films for interconnect capacitance analysis using CLEVER. The simulation is run in 2D

Requires: CLEVER This example demonstrates the analytical local oxidation model (LOCOS) included in CLEVER. Oxidation can be included in the process flow to more accurately model the geometry around the

Requires: CLEVER This example is a six-transistor, three metal, single poly SRAM cell. The cell consists of four NMOS and two PMOS transistors. The layout file defines various layers up

Requires: CLEVER, VICTORYPROCESS Minimum Versions: Clever 3.10.13.A, VictoryProcess 7.7.6.A This example creates the same SRAM design as in clex16, but uses the Victory Process simulator to create a more realsitic