Requires: CLEVER

An inverter is one of the most common cells found in layouts. This example contains one inverter cell designed with 4 NMOS and 4 PMOS transistors. It is an illustration of how Clever inserts auxilliary nodes, as in example clex05.in, where necessary into the layout. The back-annotated layout may then be re-plotted in MaskViews. The etching process in this example is the simplest manhattan type.

This example has been used in the CLEVER tutorial in the manual and more information on it can be found there.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Output Results

These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation
you should consider updating to a later version of the software.

Input Files

Input Deck

go VictoryProcess

## Process Description ##

Init Layout=clex08.lay Depth=1 Material=Silicon RuleFile=clex08.lmp 

Deposit Material=Oxide Thickness=0.25 Max

Deposit Material=Polysilicon Thickness=0.3 Max
Etch Material=Polysilicon Thickness=0.3 Max Mask=POLY
Electrodes Mask=POLY Material=Polysilicon
Electrodes Mask=*GATE Material=Polysilicon

Deposit Material=Oxide Thickness=0.25 Max
Etch Material=Oxide Thickness=0.9 Max Mask=VIA2 Reverse
Electrodes Mask=*CONT Material=Silicon

Deposit Material=Aluminum Thickness=0.25 Max
Etch Material=Aluminum Thickness=0.25 Max Mask=MET1
Electrodes Mask=MET1 Material=Aluminum

Deposit Material=Oxide Thickness=0.25 Max
Etch Material=Oxide Thickness=0.3 Max Mask=VIA3 Reverse

Deposit Aluminum Thickness=0.5 Max
Etch Material=Aluminum Thickness=0.6 Max Mask=MET2
Electrodes Mask=MET2 Material=Aluminum

Deposit Oxide Thickness=0.25 Max

Save Name=clex08_0

go victorymesh 
load in= clex08_0
remesh delaunay
refine region="silicon,sio2" max.size=0.2
save out=clex08_1 mode="clever" 

go clever

Init Layout="clex08.lay" Depth=1 Map="clex08.lmp" Structure="clex08_1.str" 

Save Spice="clex08.before.net"

## After creating the 3D structure   ##
## Perform the Interconnect Analysis ##

Interconnect Adapt=(0.04, 0.02)

Save Spice="clex08.net"
quit