Customers

Power management IP: LDO regulators and voltage references Silvaco power management IP gives your TSMC 3 nm N3P design two LDO regulators and a bandgap reference, so every block on

Embedded processor IP: ColdFire and 8051 cores Put a 32-bit ColdFire core or an 8-bit 8051-compatible core into your SoC. Silvaco licenses this embedded processor IP as synthesizable Verilog, either

MIPI M-PHY IP: high-speed serial physical layer If your SoC needs UFS flash storage or a chip-to-chip link, Silvaco’s MIPI M-PHY IP gives you an M-PHY v4.1 physical layer running

MIPI C-PHY IP: three-phase symbol encoding physical layer Silicon-proven MIPI C-PHY IP, built by Mixel and now part of Silvaco, for IC designers who need CSI-2 camera or DSI display

MIPI D-PHY IP: CSI-2 and DSI physical layer Silicon-proven D-PHY transmitters, receivers and Universal PHYs for your camera and display links, from the Mixel team that took D-PHY to real

MIPI I3C interface IP: controller and target cores Configurable I3C interface IP for SoC teams moving their sensors onto one two-wire bus: five controller and target cores from Silvaco, delivered

Automotive IP: CAN, CAN-FD, LIN and FlexRay protocol controllers Silvaco’s automotive IP gives your SoC team synthesizable CAN, CAN FD, LIN and FlexRay controllers, proven in use under ISO 26262

AMBA IP cores and subsystems: AXI, AHB and APB Silvaco’s AMBA IP gives your SoC team all three buses: AXI, AHB and APB controllers and peripherals, the fabric and bridges

Foundation IP: standard cells, memory compilers and interface IP Foundation IP you license rather than build: standard cell libraries, memory compilers and I/O, characterized on named foundry processes and tuned

IP testability: full-speed internal loopback for PHY IP Mixel D-PHY transmitters and receivers, now part of Silvaco, that check their own link at full data rate inside your SoC, on

LVDS IP: Low-Voltage Differential Signaling PHY LVDS IP designed by Mixel, now part of Silvaco: a four-channel, TIA/EIA-644-compatible serializer and deserializer pair for SoC teams whose chips talk to an

Multi-Standard SerDes IP: Combo and Configurable PHY Multi-standard SerDes IP from Mixel, a Silvaco company, for when your SoC has to speak more than one interface standard. Talk to an