Simulation Standard

Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between SmartSpice and the Analog Artist Electrical Design System and Composer Design

The intrinsic capacitance parameter extraction routine (INTCAP) is in the CAP analysis section of the UTMOST III MOS module (Routine#67). The INTCAP routine has 5 different intrinsic cap measurements and

Q: I often use the temporary reference point, but I would like to see both absolute coordinates and relative coordinates, without toggling the reference point on and off.

This paper concerns the problem of determining optimal placement of rectangular blocks within a rectangular area known as the packing or cutting-stock problem. This problem arises at then floorplanning stage

Guardian is a (state-of-the-art) hierarchical netlist comparison system, which eliminates many of the disadvantages of existing programs. Running on PCs under Windows NT, it easily compares circuits with a large

This article presents Single Event Upset (SEU) simulation of a SRAM cell using MixedMode3D. MixedMode3D provides the capability to simultaneously perform circuit simulation coupled with three-dimensional device simulation. This allows

A new diffusion algorithm based on a Galerkin method with linear finite elements, an extremely fast sparse matrix solver, and object oriented physical modeling is one of the new features

A. Typically, UTMOST III s-parameter module is used to measure the FT versus IC (collector current) characteristic of bipolar transistors. The FT_CE routine can also be utilized to extract important

Several enhancements have been made to the TFT models in SmartSpice. New parameters have been added to improve accuracy and allow simular sophisticated modeling options to MOS.

When performing statistical analyses it is often necessary to compute transformations of the observed data. This transformation may only involve a single parameter, or it may be a complicated function