Casey Molver

This article focusses on the use of Silvaco International’s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is a standard language used for behavioral level modeling.

This simulation standard will discuss Silvaco International’s post processing application SmartView and will highlight features that identifying it as an important tool to the design engineer. In particular, the integration

The transient simulation uses an adaptive time-stepping algorithm depending on the change in the circuit waveforms (dV/dT). This means the simulated waveform consists of uneven time steps (more time points

DRC Guard Performs "real-time" DRC on Expert Layout Editor. DRC Guard’s real-time design rule check (DRC) verifies entered or modified objects after the objects are edited. DRC Guard detects and

Silvaco’s Expert tool is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase designer productivity by adding enormous flexibility and efficiency

The article "Connectivity options for DRC spacing check operations in Guardian" (Simulation Standard, vol. 11, no. 12) [1] describes layout netlist connectivity based on DRC checks. Earlier versions of Silvaco

We have lots of cells that become off-grid when we do cut-and-paste from other cells. We tried to use the "Tools->Snap Selected to Grid" command, but the cell doesn't get

A great deal of recent industry attention has focused on the use of non-planar multi-gate device structures in future generation MOS devices that feature channel lengths below about 50 nm

In order to investigate the influence of ridge separation on the transverse optical modes of a double ridge edge multiple quantum well (MQW) emitting laser, we have designed a generic

The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical effects, which are observed as shifts in threshold

It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor materials. Typically a heterojunction bipolar transistor (HBT) consists

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will