Abstract
Traditional physics-based process and device simulation provides detailed insight into semiconductor process and device behavior, but its computational cost and specialist setup requirements can limit broader use. This article presents an Fab Technology Co-Optimization (FTCO™) workflow that converts calibrated structural and electrical simulations into compact, interactive surrogate models. Smart design of experiments efficiently samples the parameter space, while automated extraction prepares geometry interfaces, scalar responses, and electrical curves for modeling in Victory Analytics. Structural surrogates enable real-time exploration of process geometry; parametric surrogates support sensitivity analysis, multi-response optimization, and Monte Carlo estimates of variability and Cp/Cpk; and curve surrogates reproduce complete characteristics such as MOSFET Id-Vg curves. In the illustrated MOSFET case, simulation of a surrogate-predicted optimum agreed with all modeled parameters to within 3%. Portable XML model cards allow validated models to be shared across Windows and Linux environments, extending predictive simulation insight to process, device, fab, and product engineering teams.
View the companion webinar: AI-Powered Surrogates: From Process Geometry to I-V Curves