Requires: SmartSpice & Smartview

Minimum Versions: SmartSpice 3.16.12.R

A simple buffer with input/output signals is required.

• No example available at the moment.

Input Files

buffer_test.in

Silvaco test deck for series_switch buffers
**********************************************************************
.OPTION d_ibis='./IbisLibs' node
.OPTIONS NOMOD
**********************************************************************
Vin1 in1 gnd DC 2.5V PWL (0 2.5V 5n 2.5V 20n 0.0V 30ns 0.0V 40n 2.5V 50.0n 2.5V)
Tl in2 gnd out1 gnd  z0=75 td=1n
Rl out1 gnd 50
Cl out1 gnd 10p
BSW1 in2 in1
+ file= '3vt3306l_25v.ibs'
+ model = 'SWITCH1'
**********************************************************************
.TRAN 0.01ns 50.0ns
.save all
.MEAS TRAN td_fall DELAY V(in1)  VAL=0.5 FALL=1
+                  TARG  V(out1) VAL=0.5 FALL=1
.MEAS TRAN td_rise DELAY V(in1)  VAL=0.5 RISE=1
+                  TARG  V(out1) VAL=0.5 RISE=1
.end

pinmapping.in

* testing Ibis component support with pin mappings

.control
run
show bin ben bout bc.47 bc.1 bc.2
.endc

.DC Vout -0.3 3.6 0.1 LIST Vin 0.0 3.3

Vin  in  gnd 0.0
Ven  en  gnd 3.3
Vcc  vcc gnd 3.3
Vout out gnd 0.0

* component
bc en en en en
+  in in in in in in in in
+  in in in in in in in in
+  out1 out2  out3  out4  out5  out6  out7  out8
+  out9 out10 out11 out12 out13 out14 out15 out16
+  gnd gnd gnd1 gnd2 gnd gnd gnd gnd vcc vcc vcc vcc
+typ=min
+component='LVT162244'
+file='IbisLibs/LVT162244.ibs'
+power=on buffer=input $ useless parameters: ignored

.connect bc.1.out  bc.2.en  bc.3.en  bc.5.en  bc.6.en
.connect bc.24.out bc.8.en  bc.9.en  bc.11.en bc.12.en
.connect bc.25.out bc.13.en bc.14.en bc.16.en bc.17.en
.connect bc.48.out bc.19.en bc.20.en bc.22.en bc.23.en

.connect bc.47.out bc.2.in
.connect bc.46.out bc.3.in
.connect bc.44.out bc.5.in
.connect bc.43.out bc.6.in
.connect bc.41.out bc.8.in
.connect bc.40.out bc.9.in
.connect bc.38.out bc.11.in
.connect bc.37.out bc.12.in
.connect bc.36.out bc.13.in
.connect bc.35.out bc.14.in
.connect bc.33.out bc.16.in
.connect bc.32.out bc.17.in
.connect bc.30.out bc.19.in
.connect bc.29.out bc.20.in
.connect bc.27.out bc.22.in
.connect bc.26.out bc.23.in

.param rload = 100

Rout1 out1 out 1
Rout2 out2 gnd rload
Rout3 out3 gnd rload
Rout4 out4 gnd rload
Rout5 out5 gnd rload
Rout6 out6 gnd rload
Rout7 out7 gnd rload
Rout8 out8 gnd rload
Rout9 out9 gnd rload
Rout10 out10 gnd rload
Rout11 out11 gnd rload
Rout12 out12 gnd rload
Rout13 out13 gnd rload
Rout14 out14 gnd rload
Rout15 out15 gnd rload
Rout16 out16 gnd rload

* buffers
bin io=in out=intout pc=vcc gc=gnd
+power=off
+typ=min
+component='LVT162244'
+pin='47'
+file='IbisLibs/LVT162244.ibs'
ben io=en out=inten pc=vcc gc=gnd
+power=off
+typ=min
+component='LVT162244'
+pin='1'
+file='IbisLibs/LVT162244.ibs'
bout io=out1bis in=intout en=inten pc=vcc gc=gnd pu=vcc pd=gnd
+power=off
+typ=min
+component='LVT162244'
+pin='2'
+file='IbisLibs/LVT162244.ibs'

Rout1bis out1bis out 1

.print i(Rout1) i(Rout1bis)

.end