Requires: SmartSpice & Smartview

Minimum Versions: SmartSpice 4.6.8.R

This example shows how to use multiple Verilog-A modules in a simulation and to reference parameters of the module from the input deck.

This input deck consists of an sinewave source into a chain of 3 verilog-A resistor modules in series and then terminated by a spice element resistor and capacitor in parallel to ground. Internal resistance of the verilog-A module res_1 , res_2 and res_3 is set by the YVLG instance parameter that matches the parameter used in the verilog-A module (parameter ‘R’).

The output waveform
shows the signal after each stage and finally charging the RC load components.

Graphics

Input Files

resistor_1.va

//Resistor

`include "discipline.h"
`include "constants.h"

module res_1(n1, n2);
   inout n1, n2;
   electrical n1, n2;

   parameter real  R = 100.0;

   analog begin
//	$debug("Res_1=%f\n", R);
      I(n1, n2) <+ V(n1, n2)/R;
   end
   endmodule

resistor_2.va

//Resistor

`include "discipline.h"
`include "constants.h"

module res_2(n1, n2);
   inout n1, n2;
   electrical n1, n2;

   parameter real  R = 100.0;

   analog
      I(n1, n2) <+ V(n1, n2)/R;
   endmodule

resistor_3.va

//Resistor

`include "discipline.h"
`include "constants.h"

module res_3(n1, n2);
   inout n1, n2;
   electrical n1, n2;

   parameter real  R = 100.0;

   analog
      I(n1, n2) <+ V(n1, n2)/R;
   endmodule

resistor_chain.in

** 3 Resistor chain test case

.option nomod nodeck
.param r1=20 r2=50 r3=100
.ic v(out)=0
.hdl "resistor_1.va"
.hdl "resistor_2.va"
.hdl "resistor_3.va"
*v01 vcc 0 dc 5
*v02 in 0 pulse(0 5 1u 1n 1n 1u 2u)
V1 in 0 sin( 2.5 2.5 1meg)
C1 out 0 0.1u
R1 out 0 100k
*
YVLG_res_1 in  n1  res_1 R='r1'
YVLG_res_2 n1  n2  res_2 R='r2'
YVLG_res_3 n2  out res_3 R='r3'

.tran 1n 10u

**.iplot v(in)
**+   'v(out)+10'
.probe all

.end