ROM Compiler
ROM Compiler
Silvaco’s ROM compiler builds via-programmed embedded ROM IP to the size and mux your SoC needs, with zero leakage in the memory array.
How the ROM compiler keeps
die area and leakage down
You set the size and the mux. The compiler builds the instance to fit. Your floorplan never works around a fixed macro picked from a list.
Bitcell and architecture
All stored data sits on via 1, one programming layer, so the bitcell stays small and the die costs less. The cells are ultra-high density, on a compact via architecture. Silvaco verifies the design for local and global variation and mismatch, so yield holds.
Performance
Reads are fast. The compact via structure cuts stray capacitance, and dynamic power drops with it.
Leakage
None in the memory array, minimal in the periphery. On a battery-powered part, that’s battery life you keep.
Flexibility
Pick a mux option from 8 to 128 and set the address range your floorplan calls for. Need something outside the standard ranges? The compiler team tunes instances to your area, power and performance targets.
Process coverage
Available from 180 nm to 22 nm: 180, 152, 130, 110, 90, 85, 65, 55, 40, 28 and 22 nm. Silvaco covers G, LP and SOI CMOS variants, plus eFlash, BCD and high-voltage processes. If your node isn’t listed, ask about a port.
Where embedded ROM fits in your design
Boot code and firmware storage
Code fixed at tape-out, held in one via layer
Lookup tables and constants
Tables and coefficients read fast from a dense array
Battery-powered and IoT designs
No array leakage while the device sits idle
Cost-sensitive designs where die area matters
High-density cells and one programming layer keep the macro small
Silicon-proven, with part numbers you can check
25 years
of compiled memory design behind the ROM compiler
Millions of wafers
from thousands of designs on Silvaco compiled memory
12 foundries and IDMs
where Silvaco memory compilers are deployed
180 to 22 nm
the node range the ROM compiler covers
Liberty · LEF · GDSII
with every fully characterized, DRC/LVS-clean instance
ROM compilers with published part numbers
Sizes in bits. Both processes also carry dual-port SRAM compilers, if you need writable memory beside the ROM.
Guide · PDF
Summer 2026
Silvaco IP product selection guide
Both ROM compilers by foundry, node and part number, with size ranges, mux options and supply voltages.
Webinar
Summer 2026
How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
The SRAM, register file and ROM compilers, and how they're built for ultra-low power.
News
Summer 2026
Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS
The ROM, SRAM and register file compilers that came with the deal. More than 25 years of high-density, ultra-low-power design sits behind them.
Check your foundry and node with an
IP specialist
Bring your foundry, your node and the ROM you have in mind. You’ll find out whether a
compiler already runs on that process, and what a port would take. Licensing and evaluation
questions go to the same person.
ROM compiler questions
What is a ROM compiler?
A ROM compiler generates embedded read-only memory instances to a configuration you set, such as size and mux. Manufacturing fixes the stored data. Silvaco's ROM compiler outputs fully characterized, DRC/LVS-clean via-programmed ROM for your foundry process. Liberty, LEF and GDSII views come with it, ready for your flow.
What does Via 1 programmable mean?
On via 1, the layer connecting the first two metal layers, each bit is a via placed or left out. All the stored data lives in that one layer. Silvaco pairs it with a compact via architecture and ultra-high-density cells. Together they keep the footprint small, which is the point of choosing via ROM.
Why does a single programming layer reduce cost?
Only one layer carries the data, so the bitcell stays very dense. A ROM of a given size takes less silicon. Less area per macro means a smaller die, and a smaller die costs less to make. That's why via ROM suits designs where die area drives the budget.
What are the leakage characteristics?
Zero in the memory array and minimal in the periphery. The compact via architecture also cuts stray capacitance, which lowers dynamic power without slowing reads. In a battery-powered or IoT design, the ROM takes very little from the battery between wake-ups.
Which nodes and processes are supported?
The ROM compiler is available from 180 nm down to 22 nm. That covers G, LP and SOI CMOS plus eFlash, BCD and high-voltage processes. Two compilers carry published part numbers today: 61255 on TSMC 40 nm ULP eFlash and 61262 on TSMC 55 nm ULP eFlash. Node not listed? Ask an IP specialist about a port.
How many mux options are available?
Mux options run from 8 to 128 on both published compilers. The address range is flexible too, so the macro's shape can suit your floorplan. The 40 nm compiler generates ROMs from 1k to 1,152k bits. The 55 nm compiler covers 512 to 512k bits.
Related IP
SRAM Compiler
Single- and dual-port SRAM, with several low-power modes
Register File Compiler
1-port and 2-port register files
Memory Compilers
SRAM, register file and ROM in one compiler family
Foundation IP
Standard cells, memory compilers and interface IP