D-PHY RX+
Mixel D-PHY RX+: D-PHY receiver with full-speed loopback test
D-PHY RX+ is a MIPI D-PHY receiver that carries its own simplified transmitters, so your SoC’s camera or display input can be tested at full speed on the production line and again in the field.
D-PHY RX+ parts
RX+ comes as a standalone D-PHY receiver at TSMC 28HPC+ and inside C-PHY/D-PHY
combo receivers at N5, N6 and 16FFC. Designing the sending end instead? You want D-PHY
TX+.
| FOUNDRY | PART NAME | FEATURES |
|---|---|---|
| TSMC | D-PHY CSI-2 RX+ in TSMC 28HPC+ | Supports MIPI D-PHY, 2L, 1.5Gbps, full-speed internal loopback testability |
| TSMC | C-PHY/D-PHY Combo CSI RX+ in TSMC N5 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps, full-speed internal loopback testability |
| TSMC | C-PHY/D-PHY Combo CSI-2 RX+ in TSMC N6 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 6.0Gsps/4.5Gbps, full-speed internal loopback testability |
| TSMC | C-PHY/D-PHY Combo DSI RX+ in TSMC 16FFC | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/6.5Gbps, full-speed internal loopback testability |
L is a D-PHY data lane and T a C-PHY trio, with rates per lane or per trio. For every D-PHY or combo part, RX+ or not, see
MIPI D-PHY and C-PHY/D-PHY Combo. Process not listed? Talk to an IP specialist.
Applications
Wherever a receiver fault would otherwise hide behind the device feeding it.
Production test of D-PHY receivers
Every lane tested at full data rate on the production line, without a Universal PHY’s unused transmitters
Silicon bring-up
In-system diagnostics on the receive side while first silicon comes up on the bench
Designs with no external tester access
The loopback stays in the finished system, so you can recheck the receiver in the field
Proof you can check
Mixel has worked inside the MIPI Alliance since 2006. The RX+
numbers are Mixel’s own measurements.
4 TSMC nodes
N5, N6, 16FFC and 28HPC+, on the Silvaco catalog
~35% · ~50%
less area and less leakage power than a D-PHY Universal
US 10,289,511
Mixel’s patent on the RX+ implementation
100%
coverage of the whole IP, per Mixel
Customer · Mixel MIPI D-PHY IP
November 2025
indie
indie designs radar front-end modules and MMICs for cars. Its ASIL-B MIPI D-PHY CSI-2 TX and RX IP came from Mixel, built for AEC-Q100 Grade 1 and fully characterized to MIPI’s D-PHY Conformance Test Suite, with functional safety documentation.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability. We are looking forward to our continued collaboration.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
Silvaco PRO IP catalog
Each RX+ part with its foundry, node, part number and standard, next to everything else in PRO IP.
Technical detail · mixel.com
Mixel D-PHY RX+
Specifications for the RX+ configuration, and how it compares with D-PHY Universal.
Technical detail · mixel.com
Mixel IP testability support
Both testability configurations, plus the MIPI FPGA platform Mixel offers for bring-up.
Press release
March 2026
Mixel MIPI PHY IP now available as PRO IP
D-PHY, C-PHY and the combo PHY, each as TX, RX, TX+, RX+ and Universal.
Find the RX+ part for your chip
Send an IP specialist your foundry, node and the link your chip receives, and ask for
the D-PHY RX+ datasheet. You’ll hear which part fits and how licensing works.
Questions about D-PHY RX+
What is D-PHY RX+?
It’s Mixel’s MIPI D-PHY receiver in its testable form, for links running CSI-2, DSI or DSI-2. A few simplified transmitters inside the PHY give the receiver a full-speed self-test you can run on the tester and again in the shipped product, without the extra area a D-PHY Universal costs. Mixel is part of Silvaco.
What is full-speed internal loopback on a receiver?
The simplified transmitters send test patterns into each receiver lane at full data rate. The loop stays inside the PHY, clear of the serial pins, and adds almost no load to the link’s connection. Mixel puts coverage of the whole IP at 100%.
How does RX+ pair with TX+?
They test opposite ends of the same link. D-PHY TX+ adds a receiver to a transmitter, and RX+ adds simplified transmitters to a receiver, so you pick the one that matches your chip’s side. TX+ saves roughly 30% of a Universal’s area; RX+ saves roughly 35%.
Does it cost area or power?
Less than the usual route. On a traditional D-PHY, a full-speed test means building in the Universal version and carrying transmitters that sit idle in normal use. Mixel measures RX+ at about 35% less area and about 50% less leakage power than Universal. For the overhead against a plain D-PHY receiver on your process, ask an IP specialist.
Which parts include RX+?
The Silvaco catalog lists a D-PHY CSI-2 RX+ at TSMC 28HPC+, plus C-PHY/D-PHY combo RX+ parts for CSI, CSI-2 and DSI at TSMC N5, N6 and 16FFC. Each one lists full-speed internal loopback testability among its features. RX+ is also available for standalone MIPI C-PHY.
Which foundries and nodes are available?
Today’s catalog parts are all at TSMC: 28HPC+ for the D-PHY-only receiver, and N5, N6 and 16FFC for the combo receivers. That’s four processes at one foundry. Working at another foundry or node? Tell an IP specialist which one, and ask what RX+ availability looks like there.
Related
D-PHY TX+
The transmitting end, with a receiver built in for full-speed loopback test.
Testability
Mixel’s TX+ and RX+ configurations, side by side.
MIPI D-PHY
Every D-PHY part, in each implementation from plain TX to Universal.
C-PHY/D-PHY Combo
One PHY for either standard, combo RX+ parts included.