LVDS Deserializer
LVDS Deserializer IP
An LVDS deserializer from Mixel, a Silvaco company, for the SoC that sits at the far end of the link and needs its four serial channels back as parallel data.
What the LVDS deserializer does
It takes what the transmitter sent and gives your logic the parallel words it started as.
What comes out the other side
Four receive channels, built in digital CMOS and compatible with TIA/EIA-644. Clock it anywhere from 25 to 165 MHz, then choose 7 or 10 bits of parallel output per channel.
Less to build around it
Margin is the thing a receiver never has enough of. Each data channel is matched to the clock channel. That buys the receiver as much margin as Mixel can give it, and it makes the design easier to carry to a new process. The PLL is on-chip and needs no external components. Neither does anything else. There’s a power-down mode for idle time, and low-swing signaling keeps EMI down.
Listed on TSMC 40LP
The part is rated 1000 Mbps on every channel. For the transmit end of the same link, see the LVDS Serializer. If the input also has to take MIPI D-PHY, the D-PHY / LVDS Combo RX handles both.
LVDS deserializer parts
Start with the foundry and process you’re committed to.
| FOUNDRY | PART NAME | FEATURES |
|---|---|---|
| TSMC | LVDS RX in TSMC 40LP | Supports LVDS, 4CH, 1000Mbps |
CH is the channel count, and the rate is per channel. The part comes in commercial, industrial and automotive grades.
Need a process or configuration that isn’t listed? Talk to an IP specialist.
Applications
Where you’d put an LVDS input.
Display transmit links
Bringing a display stream into your SoC over four LVDS channels
Automotive display receivers
In-vehicle displays, one of the markets Mixel production-ready IP is built for
Industrial panel drivers
Controllers that take their image data over LVDS
Proof you can check
TSMC 40LP
where the listed part is built
4CH · 1000 Mbps
four channels, 1000 Mbps on each
TIA/EIA-644
the LVDS standard it's compatible with
Automotive grade
available beside commercial and industrial, as part 20X331A
Catalog · PDF
Summer 2026
PRO IP product selection guide
Every LVDS part by foundry, node, part number and grade, listed beside the serializers and the rest of PRO IP.
Product page · mixel.com
Summer 2026
Production-ready Mixel IP from Silvaco
How Mixel's PHY portfolio became available as Silvaco PRO IP, with the D-PHY/LVDS combo offered as both TX and RX.
Ask about your foundry and node
Tell an IP specialist which process you’re designing for. You’ll hear back on whether
the LVDS deserializer is offered there and what licensing involves.
Questions about LVDS deserializer IP
What is an LVDS deserializer?
An LVDS deserializer sits at the receiving side of an LVDS link. It converts the link's serial channels back into the parallel data your chip works with. Silvaco's version is Mixel's four-channel design: digital CMOS, TIA/EIA-644 compatible, and listed today on TSMC 40LP.
How does it pair with a serializer?
The serializer packs parallel data onto four LVDS channels at the transmit end. The deserializer unpacks it where the link lands. Silvaco lists one of each on TSMC 40LP, an LVDS TX and this RX, both rated 1000 Mbps per channel. You'll also find the serializer on UMC 40ULP.
Which foundries and nodes are available?
Today there's one listed part, on TSMC 40LP. It comes as part 20X331 in commercial and industrial grades, or 20X331A in automotive grade. Mixel matches the data and clock channels partly to ease process migration, so a different foundry or node is worth raising early. An IP specialist can tell you what a move to your process would take.
What data rates are supported?
The TSMC 40LP part is rated 1000 Mbps per channel, four channels wide. Mixel puts the deserializer core itself at up to 1.15 Gbps of bandwidth and 5 Gbps of total throughput. If your link needs more than the listed part delivers, ask about the core.
How many lanes are supported?
Four, though LVDS calls them channels. This deserializer receives four data channels plus a clock channel, and each data channel delivers a 7- or 10-bit parallel word. Designs that also need MIPI D-PHY lanes should look at the D-PHY / LVDS Combo RX, which takes both.
How does this differ from a MIPI D-PHY receiver?
They receive different standards. A D-PHY receiver carries MIPI camera or display traffic (CSI-2 or DSI) over one to four data lanes. This one takes TIA/EIA-644 LVDS across four channels. For an input that has to accept both, Silvaco lists an LVDS/D-PHY CSI-2 RX combo on TSMC 28HPC+.
Related
LVDS Deserializer
The transmit side, listed on TSMC 40LP and UMC 40ULP
LVDS
Both ends of the link, and where LVDS sits next to MIPI
D-PHY / LVDS Combo RX
Takes LVDS or MIPI D-PHY on one input, on TSMC 28HPC+
D-PHY / LVDS Combo TX
Drives LVDS or MIPI D-PHY from one transmitter