LVDS
LVDS IP: Low-Voltage Differential Signaling PHY
LVDS IP designed by Mixel, now part of Silvaco: a four-channel, TIA/EIA-644-compatible serializer and deserializer pair for SoC teams whose chips talk to an LVDS panel, camera or industrial device.
Two ends of one LVDS link
Put the serializer on the sending side of the link and the deserializer on the receiving side.
Each runs four channels. Three parts are ready to license today, two at TSMC and one at UMC.
LVDS Serializer
Sits in your transmitting chip. Parallel data enters at a width you set and leaves serialized across four LVDS channels, clocked anywhere from 25 to 165 MHz. Optional pre-emphasis buys extra reach without giving up a low bit-error rate.
Two parts on the catalog. TSMC 40LP runs 1000 Mbps per channel; the UMC 40ULP TX+ adds full-speed internal loopback testability. Both ship in commercial, industrial and automotive grades.
LVDS Deserializer
At the receiving chip, it rebuilds the four LVDS channels into parallel data, 7 or 10 bits per channel. Clock and data paths are matched to keep margin at the deserializer.
A single part, on TSMC 40LP, running 1000 Mbps per channel in all three grades.
Need MIPI D-PHY on that same interface too? A D-PHY/LVDS combo PHY handles both.
Pick D-PHY/LVDS Combo TX or D-PHY/LVDS Combo RX from the Multi-Standard family.
Production-ready today
Part numbers, processes and grades your qualification team can
check against the published catalog.
3 parts
two serializers, one deserializer
TSMC 40LP · UMC 40ULP
the two processes they're on today
1000 Mbps
per channel on the TSMC 40LP parts, four channels wide
TIA/EIA-644
the LVDS standard they're compatible with
Automotive grade
offered on all three, as are commercial and industrial
Catalog · PDF
Summer 2026
PRO IP Product Selection Guide
Every LVDS part sorted by foundry and node, with part numbers and grades, and the D-PHY/LVDS combos listed alongside.
Press release
March 2026
Mixel MIPI PHY IP, production-ready from Silvaco
Covers the MIPI D-PHY/LVDS combo, one PHY that switches between both standards and is TIA/EIA-644 compatible.
Is LVDS IP available on your process?
Name your foundry, your node and the device on the far end of the link. An IP
specialist will tell you which Mixel LVDS part matches and whether it already runs in
silicon on that process. Licensing comes after that, once you know it fits.
Questions engineers ask about LVDS IP
What is LVDS?
LVDS stands for low-voltage differential signaling. Each bit travels as a small voltage difference between two wires, which keeps power and EMI low, and TIA/EIA-644 defines the standard. Mixel designed Silvaco's LVDS IP as a four-channel pair, a serializer plus a deserializer, in digital CMOS.
When is LVDS used instead of MIPI?
Pick LVDS when the device across the link expects it, for instance an LVDS display panel. It's a separate standard, TIA/EIA-644, rather than a MIPI specification. If your design has to serve LVDS and MIPI devices alike, a D-PHY/LVDS combo PHY covers both.
What is the difference between a serializer and a deserializer?
One sends, one receives. The serializer lives in the transmitting chip and packs parallel data, at a width you program, onto four LVDS channels. At the other end, the deserializer unpacks those channels into parallel data again, 7 or 10 bits per channel.
Which foundries and nodes are available?
Two processes today: TSMC 40LP carries a serializer and a deserializer, and UMC 40ULP carries a serializer with full-speed internal loopback testability. Every part is offered in commercial, industrial and automotive grades, and if you're on another process, ask an IP specialist before ruling LVDS out.
Can LVDS and D-PHY share one interface?
Yes: a D-PHY/LVDS combo PHY switches between the two standards on a single PHY. Silvaco's catalog has combo transmitters for GlobalFoundries 22FDX+ and Tower 65BSB, plus a combo receiver for TSMC 28HPC+. You'll find all three in the Multi-Standard family.
What data rates are supported?
On TSMC 40LP, the serializer and the deserializer both reach 1000 Mbps per channel over four channels. For the LVDS design itself, Mixel quotes up to 5 Gbps aggregate throughput and an input clock between 25 and 165 MHz.
Related IP
LVDS Serializer
Transmit-side IP on TSMC 40LP and UMC 40ULP
LVDS Deserializer
Rebuilds parallel data at the receiving chip
D-PHY/LVDS Combo TX
A transmitter that speaks LVDS or MIPI D-PHY
D-PHY/LVDS Combo RX
Combo receiver, on TSMC 28HPC+
MIPI IP
D-PHY, C-PHY and M-PHY physical-layer IP