Minimum Required Version: Expert 4.10.39.R Device link improves the efficiency of layout design of CMOS logic circuits. By overlapping diffusion areas of MOSFET parameterized cells (PCells) that have a common

Minimum Required Version: Expert 4.10.39.R When routing an NDL (Netlist Driven Layout) circuit in Expert, using the flight lines tool greatly simplifies the process and can help to verify that

Minimum Required Version: Expert 4.10.39.R The Node Probing feature highlights (selects) all layout objects electrically connected with a given object. It is designed to trace electrically connected nodes throughout the

Minimum Required Version: Expert 4.10.39.R Expert’s node-probing is very useful in a hierarchical layout design. It traces connections through the cell hierarchy without any limitation. The extraction of connections becomes

Minimum Required Version: Expert 4.10.39.R Shared libraries allow users to simultaneously work on the same project across a network. This feature is very useful for teams completing large chips, by

Minimum Required Version: Expert 4.10.39.R When the Snap to pin mode is enabled in the Creating Wires command form, the cursor is automatically snapped to the nearest instance pin to

Minimum Required Version: Expert 4.10.39.R 1.0. Preliminary steps to learn about the PCell cache feature Run the Expert application Choose Libraries->Setup and add the library “simucad_demo_pcells.eld” When working with projects