The debut of Silvaco's new schematic editor, Scholar, is drawing closer. Scholar is a sophisticated design tool which derives its power and flexibility from the fact that it is built

In collaboration with STMicroelectronics Central R&D at Crolles (France), a new routine has been developed in UTMOST III to provide a complete solution for MOS Philips Model 9 parameter extraction.

The .ALTER statement is designed to allow a SPICE input deck to be re-run with a change in a single parameter. This feature is especially useful in characterization. For this

I run DRC, find one-two violations, correct them, then I re-run DRC to check whether my corrections worked. However re-running on the whole design is time-consuming. How can I run

Rectangular partitionings form a mathematical base for many modern approaches to automation of VLSI design [1-3]. In particular, popular methodologies of hierarchical placement (by cell grouping / merging) as well

In this paper we introduce one of the latest and most advanced features of Silvaco's Expert Layout processor for Windows NT ­ DRC Guard. DRC Guard is fully functional real-time

When using the analytical implant tables in ATHENA the default model for the lateral implant range assumes a gaussian profile with a standard deviation equal to the vertical standard deviation

The shrinking critical dimensions of modern technology place a heavy requirement on optimizing the etching of narrow mask opening. In addition the aspect ratio of etches has been increased requiring

The ATLAS device simulation framework has been to improve the analysis the large signal transient behavior. These features include a simple specification for single frequency sinusoidal waveforms and frequency domain

CLEVER is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process simulator is used to realisticly reproduce the