How to Model and Simulate Flat Panel Pixel Arrays
To design a flat panel, first you need to understand the functionality of the driving device in the pixel and then the pixel functionality in the large array. In this webinar we will look at some of the effects to check when designing a flat panel:
- TFT driving device characteristics
- Pixel unit operation and timing
- Timing in a large array of Pixels and scene changes
- How active devices are used and the constraints
Presenter
Colin is a Chartered Engineer with over 30 years of experience in the semiconductor industry. He has worked on production/development of device process for both silicon and III-V compounds as well as device/circuit design covering test structure, SRAM, IGBT, and SAW filters. He has characterized a wide range of devices including low power, RF, radiation hardened, and power devices used in passenger trains. He is currently Silvaco’s Compact Modeling Coalition (CMC) and Si2 representative and he is active in the simulation of the latest circuit devices. Colin has a BSc(Hons) in Physics from the University of Surrey.
WHO SHOULD ATTEND:
Circuit designer involved with designing and simulating flat panel designs.
When: May 13, 2021
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English