Testimonials

In this paper we introduce one of the latest and most advanced features of Silvaco's Expert Layout processor for Windows NT ­ DRC Guard. DRC Guard is fully functional real-time

When using the analytical implant tables in ATHENA the default model for the lateral implant range assumes a gaussian profile with a standard deviation equal to the vertical standard deviation

The shrinking critical dimensions of modern technology place a heavy requirement on optimizing the etching of narrow mask opening. In addition the aspect ratio of etches has been increased requiring

The ATLAS device simulation framework has been to improve the analysis the large signal transient behavior. These features include a simple specification for single frequency sinusoidal waveforms and frequency domain

CLEVER is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process simulator is used to realisticly reproduce the

The traditional Noise models in SPICE used two parameters (AF and KF) to model the noise level and the frequency dependency of flicker noise in MOS devices. There are three

Following the log file conversion tool for TonyPlot introduced with UTMOST 12.3.14.R1, new file formats have been added to UTMOST III's printing and plotting options to make manipulating UTMOST generated

The latest Berkeley BSIM3v3.2 model of June 16 1998 has been integrated into SmartSpice 1.5.5. The Silvaco implementation of the Berkeley BSIM3v3.2 model can be invoked by specifying the model

Silvaco now offers the EKV (ENZ, KRUMMENACHER, VITTOZ) MOSFET model version 2.6 originally developed in EPFL ("Ecole Polytechnique Federale de Lausanne" - Switzerland), as part of the SmartLib product-independent model

The latest Berkeley BSIM3v3.2 model of June 16 1998 is now available in the SmartSpice 1.5.5 release. Two BSIM3v3.2 implementations are supported in SmartSpice and UTMOST III.

Q: Can I draw tangents to circles in EXPERT? A: Expert supports several options for drawing sophisticated shapes. There are three ways to accomplish this task.

Placement and routing problems for integrated circuits are inherently interrelated and extremely complex from the algorithmic point of view. This complexity grows exponentially as the scale of integration increases.