Testimonials

It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor materials. Typically a heterojunction bipolar transistor (HBT) consists

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of Silvaco Simulation Standard. This model utilizes a new

Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to 21. SmartSpice uses version 7 by default, but

Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition is required prior to simulation. Constant disk access

One of the methods to define a Voltage Controlled Oscillator (VCO) in a SPICE simulation is to make use of a voltage-controlled voltage source (E element). A typical VCO expression

Level=36 RPI poly-Si TFT and other original TFT models do not support automatic geometry binning. The enhanced model included with SmartSpice 1.9.7.C or later now supports the selecting of a

Silvaco Expert is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase designer productivity by adding enormous flexibility and efficiency to

Modern complex circuit designs require automatic router functionality in circuit layout editors. In multi-layer hierarchical design, it is often necessary to build a single wire between two objects or arbitrary

The C++ interface for Silvaco’s Expert layout tool, is now an exclusive customization language that expands the tool’s handling of high-level customization, such as a design application working with Expert’s

After I create my round curve and run a DRC check on my design, it comes up with hundreds of errors associated with curves. For example, I have the layer

The silicon germanium heterojunction bipolar transistor (SiGe HBT) is a promising technology for combining the operating speed of compound material devices with the production capability of bulk silicon. The presence