Home > Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices

Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices

Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices

Banner Blue

Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices

Ultra-scaled Field-Effect Transistor (FET) technology requires simulations at the atomic scale for designing the most advanced technological architectures at 5 nm node and below. Thanks to Victory Atomistic’s combination of non-equilibrium Green’s functions (NEGF) and state-of-the-art band structure calculations, versatile, predictive, and fast simulations become accessible. To illustrate Victory Atomistic usage, we will use a silicon Nanowire Field-Effect Transistor (NWFET) with a small cross-section, including several electron-phonon scattering mechanisms, within the self-consistent Born approximation, and optimized by a generalized low-rank projection.

We will show how simulating NWFETs becomes easy to perform, even without full academic knowledge of the NEGF theory; the complexity is hidden inside the simulation tool which benefits from years of development at the highest level, Victory Atomistic optimization allows users to obtain a meaningful I(V) curve daily, and its integration within the Silvaco environment provides a smooth transition for TCAD users.

What You Will Learn
  • Why atomistic simulation becomes necessary at low scale
  • How to set up the Victory Atomistic TCAD environment
  • Nanowire FET: Simulation capabilities of Victory Atomistic
  • Performances, visualization of results, and extension to other configurations

Presenter

Philippe BlaiseDr. Philippe Blaise, Senior Application Engineer, Silvaco TCAD Division

Dr. Philippe Blaise has been a senior application engineer in atomistic simulation at Silvaco’s TCAD Division for three years. Prior to joining Silvaco, Dr. Blaise was a senior engineer specialized in atomistic simulation of new memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He is co-author of more than 50 papers in peer-review journals in the field and 30 contributions to conferences and workshops, plus 5 patents and one book chapter.
Dr. Blaise holds a Master’s degree in applied mathematics from ENSIMAG engineering school and a Ph.D. in solid states physics from the Université Grenoble Alpes, France.

WHO SHOULD ATTEND:

TCAD engineers and management looking for solutions to efficiently achieve ultra-fast simulations of next generation atomistic devices in advanced process geometries.

When: September 8, 2022
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English

Register!

Webinar Details

Date

Location

Language

Webinar Registration Form

Webinar Registration For Archive