Silvaco has an upcoming webinar IP Solutions for Secure Autonomous Driving on Dec. 3, 10am – 11am (PST) .The webinar will present the risks and necessary countermeasures for securing cyber-physical vehicle systems.

In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL. A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts. The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip. These 3 categories of digital design IP are called Foundation IP.

I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I/O Design and Characterization. He talks about using the Viola characterization tool from Silvaco for a complex part while under time pressure to produce an accurate model. A full ranscript of the conversation is below.