Daily Archives: 2003年6月1日
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June 1, 2003
Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.
23 years ago
HIPEX-Net: Hierarchical Layout Extractor for Expert Editor
HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted
23 years ago
“Shortest Path” Option for Flight Line Style (Net Bar)
There is the recent improvement in Expert Layout Editor, the “Shortest path” option was added to Flight line styles (Net Bar). This option allows to build the shortest tree (network)
23 years ago
Expert Layout Editor Recent Improvements: Over-the-Point Drawing of Orthogonal Shapes
This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers
23 years ago
Guardian DRC Edge Layer Operations
Recent versions of Guardian DRC introduce operations that involve edge layers, either on input or on output. An edge layer is a layer that contains line segments that are edges
23 years ago
Guardian LVS: New Platform-Independent GUI
We introduce a platform-independent version of Guardian LVS. An important feature of any tool is its capability to operate on various platforms and to support internationalization. Now Guardian LVS is
23 years ago
Counting Instances in an Expert Editor Layout
Q: I have some trouble counting the number of in-stances in a layout using Expert. I have tried to use the Chip Rover feature