Yearly Archives: 2000
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2000
Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.
26 years ago
Connectivity Options for DRC Spacing Check Operations in Savage
An IC layout has to satisfy many technological design requirements. One of these is spacing, i.e., a layout object has to be separated from another one by some minimal distance.
26 years ago
Recent improvements in Expert, Savage, Guardian and Maverick
Most of recent improvements in Expert, Savage, Guardian and Maverick are aimed at the enhancement of the usability of these tools. All features described are developed according to the requests
26 years ago
Optimal Packing of Orthoblocks For ULSI Floorplanning
Virtually all latest and prospective enhancements of Expert Layout processor (for example, semi-automatic floorplanning) are based on sophisticated geometrical models. In some cases some advanced mathematical research is necessary to
26 years ago
Hints, Tips and Solutions for Expert Layout Editor
If I try to close a project, Expert gives me a prompt: "Save changes in a project?", but I remember that I didn't do any editing of cells. When can
26 years ago
Simulating Impurity Freeze-Out During Low Temperature Operation
The low temperature operation of many device structures has been shown as an effective method for improving device performance without reducing device size. By modeling low temperature phenomena, numerical simulation
26 years ago
Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D
This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET is one of the most attractive alternative to
26 years ago
Non-Stationary Transport Effects: Impact on Performances of Realistic 50nm MOSFET Technology
We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyzes, are applied to existing devices. This work shows
26 years ago
ATLAS can be used to perform large signal sinusoidal analysis
The Atlas syntax is flexible enough to allow the definition of sinusoidal nodal voltages by defining them on the SOLVE statement line. To illustrate this the structure shown in Figure
26 years ago
RF CMOS Modeling Using UTMOST III AC (S-Parameter) Module
This article presents a high frequency SPICE model parameter extraction method for CMOS devices. Current compact MOS models are developed for low frequency applications and provide good fits for DC,
26 years ago
New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT
New improvements have been added to Shur a-Si:H and Poly-Si Thin Film Transistors models. These enhancements include self-heating effect and a new charge conservation model.