Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.
Required Modules
Victory Process
- 3D Structure Editor
Victory RCx
In this case we demonstrate how to use the Victory Process 3D Structure Editor to create the “L ” shaped metal region, often found in custom cells, which is insulated from the silicon substrate by a 0.5um oxide layer. The processing steps are very simple requiring only etching and deposition.
As is also the case with any VictoryRCx simulation the process etching steps are driven from a layout file. This file is included in the support files when this example is loaded.
The deposition model remains the relatively simple model used and described in example VRCx_ex01.in. However, for the etching process, this example has combined the non-manhattan angular etch model in example VRCx_ex02.in with the physical lithographic masking and imaging from example VRCx_ex03.in. The structure produced from this combination of models should therefore simulate reality to a much greater extent than the previous examples.
Once the process simulation is complete, the three-dimensional structure is saved with the Export statement and can be plotted.
The structure created in the Victory Process 3D Structure Editor, is then loaded into VictoryRCx and the interconnect parasitic extraction is carried out using the Interconnect statement. Firstly, however, the material parameters of silicon are defined using the Material statement so that in this case silicon “inherits ” the same material properties as oxide. In this example only the parasitic capacitance values are calculated from the field solver. During this calculation automatic mesh adaption is performed with the Adapt parameter whereby the mesh is modified until the error in the capacitance extraction is reduced to the default maximum of 5% of the capacitance. The structure and the SPICE netlist are then saved.
Images
