Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software. These examples can be used by beginners and advanced users for product evaluation, teaching purposes, and self-training.

Required Modules

Victory Process

• 2D Oxidation
• 2D Diffusion & Implantation

Victory Mesh

• 2D Meshing

Victory Device

• 2D Simulator

This example demonstrates a generic 2D process and device simulation flow that is aligned to typical industrial methods.
The process starts off with a highly doped wafer, on top, an epitaxial layer is used for the drift region, the doping and thickness of which will heavily influence our breakdown voltage.
A sacrificial oxide is thermally grown, through which the JFET and threshold voltage adjust implant is made across the entire surface.
Next a poly oxide mask stack is deposited to define the PWELL opening. After implanting the PWELL the poly oxide stack is oxidized. The distance the oxide grows out laterally will define the gate length as the thermal oxide now masks for the NPLUS source implant.
Following that, a portion of the NPLUS source implant is etched through and an implant for the PPLUS source made giving a heavily doped contact area.
Before finally growing the gate oxide and depositing the electrodes.
The processing of the device is now complete.
The structure is then remeshed ready for device simulation using a delaunay meshing scheme. It has a uniform base mesh, on top of which a number of refinement schemes are used. The interface to the channel is finely sliced (OFFSET) to ensure the channel is well meshed. For accurate breakdown voltage simulations a fine mesh around the location of the peak electric field is required. This is achieved by using junction refinement.
Moving on to device simulation, a range of SiC specific models are used. The area (WIDTH) is chosen to be typical of a 25A device. The first simulation is for the threshold voltage, the gate and drain are tide and ramped to a compliance of 25 A and then the threshold voltage was extracted at 5 mA on the drain. RdsOn is extracted at a gate voltage or 15 volts and 25 A on the drain. For breakdown voltage, the drain was ramped and the voltage extracted at 0.1pA. The decks are structured in such a way that all of the key data is automatically extracted from the simulations lowering the effort from a user point of view.

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