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1 week ago

check_ex01 : Simulating Device Characteristics

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.10.2.R, SmartView 2.28.2.R This example describes how to use the model check module to simlulate some mosfet characteristics. The

1 week ago

check_ex02 : Simulating Extracted Characteristics

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.10.2.R, SmartView 2.28.2.R This example describes how to use the model check module to simlulate and display some mosfet

1 week ago

check_ex03 : Checking for Binned Model Discontinuities

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.10.2.R, SmartView 2.28.2.R This example describes how to use the model check module to check for binned model threshold

1 week ago

cor_ex01 : Retargeting a Model Card

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 2.19.2.R, SmartSpice 5.2.0.R, SmartView 2.2207.0.R This example shows how to use the Utmost IV Corner and Retargeting module to generate an

1 week ago

cor_ex02 : Creating Corner Models

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 2.19.2.R, SmartSpice 5.2.0.R, SmartView 2.2207.0.R This example shows how to use the Utmost IV Corner and Retargeting module to generate typical,

1 week ago

cor_ex03 : Parameter Selection for Corner Model Extraction

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 2.19.2.R, SmartSpice 5.2.0.R, SmartView 2.2207.0.R This example shows how to perform the parameter selection needed in the Utmost IV Corner and

1 week ago

cor_ex04 : Creating Corner Models Using Targets with Preliminary Extraction

Requires: Utmost IV, SmartSpice, SmartView Minimum Versions: Utmost IV 2.19.2.R, SmartSpice 5.2.0.R, SmartView 2.2207.0.R This example shows how to use the Utmost IV Corner and Retargeting module to generate typical,

1 week ago

vwfex01 : Stress in MOSFET with Embedded SiGe Layer

Requires: VWF, ATHENA, This example demonstrates simulation of stresses in a test MOSFET structure with an embedded SiGe layer. All important geometrical characterisics of the test structure, including thicknesses of

1 week ago

vwfex02 : VT Optimization Using a DOE Approach

Requires: VWF, ATHENA, ATLAS The objective is to optimize 4 process parameters (gate oxide time, temperature, Vt adjust implant dose, and energy) in order to get a targetted Vt of

1 week ago

vwfex03 : VT Optimization Using an Optimization Approach

Requires: VWF, ATHENA, ATLAS The objective of this example is to optimize 4 process parameters (gate oxide time and temp as well as Vt adjust implant dose and energy) in