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1 week ago

011_inherited_nets_explicit : Inherited Nets with Explicit Pins Schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example illustrates use of inherited nets on logic symbols that have explicit pins for power, substrate, and ground (see schematic.png ). In

1 week ago

012_inherited_nets_implicit : Inherited Nets with Implicit Pins schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The illustrates using net property definitions on the symbol instances (see Example12.png ). For X1, VCC! is passed in for POWER and GND!

1 week ago

013_inherited_nets_ringosc : Inherited Nets Ring Oscillator schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a ring oscillator hierarchical schematic which illustrates the use of the netInherit symbol (see Example13.png ). This symbol is from

1 week ago

014_device_characterization : Nmos device characterization schematic

Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a testbench schematic for testing MOS models and devices (see Example14.png ). In this example, a LEVEL=1 NMOS device is

1 week ago

001_LNA : LNA schematic RF Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R Typical Low Noise Amplifier (LNA) designs utilize reasonable gain and a low noise figure to provide stability without oscillation over the useful range

1 week ago

002_mixer : RF Mixer Schematic Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R RF Example 2 is a mixer design ( mixer.png ). The three ports of the mixer are the Local Oscillator port (LO), the

1 week ago

003_freq_divider : RF Frequency Divider Schematic Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R The schematic for Example 3 ( schematic.png ) is a frequency divider design. Since the division factor is 4, the fundamental frequency is

1 week ago

001_RSFF_sim : RS Flipflop Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R The Gateway schematic front end can capture digital circuits for netlisting in the verilog format and simulating in the Silvaco SILOS simulator. To

1 week ago

002_adpll : All Digital PLL Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 2 is an all digital PLL schematic design ( all_digital_PLL.png ). In the design browser, clickING on the parameters entry displays the

1 week ago

003_one_bit_adder : One Bit Adder Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 3 is a one bit adder verilog design. The schematic ( schematic.png ) is shown consisting of gate level primitives and one_bit_adder.v