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1 week ago
001_RSFF_sim : RS Flip Flop Simulation
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This RSFF simulation is designed hierarchically with the RSFF block sitting on the top level schematic. Descending one level down, the main flip-flop
1 week ago
002_sine2square : Sine to Square Wave Converter
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This schematic example (see sine2square.png ) demonstrates a sinusoidal voltage input at a frequency of 10KHz converted to a square wave through an
1 week ago
003_1GHz_amplifier : Tuned 1GHz Amplifier Schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This schematic example ( amplifier_schematic.png ) shows a 1GHz tuned amplifier designed using the VBIC level=5 NPN bipolar model. The control file (
1 week ago
004_Chebyshev_LPF : Chebyshev Low Pass Filter schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 4 illustrates the AC magnitude response of the 2-pole Chebyshev Low Pass Filter schematic (see chebyshev_schematic.png ). The example uses the JFET-based
1 week ago
005_biquad_notch : 60 Hz Biquad Notch Filter schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 5 demonstrates the practical use of a biquad circuit configuration (see biquad.png pngview) to realize a notch filter. The four-opamp biquad circuit
1 week ago
006_current_mirror : Bipolar Current Mirror schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The amplifier design shown in current_mirror_schematic.png uses the bipolar differential pair as the main component in the circuit. Looking at R1=R2 and Q1
1 week ago
007_4th_order_butterworth_GIC : 4th Order Butterworth LPF using the GIC
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 7 is a 4th order lowpass filter design using the Generalized Impedance Converter (GIC) method (see GIC.png pngview). The GIC is practical
1 week ago
008_current_starved_VCO : Current Starved VCO schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R Example 8 demonstrates a 5-Stage VCO design using a level=54 BSim4 SmartSpice model (see schematic.png ). The circuit can be used to generate
1 week ago
009_sampling_gate : JFET Sampling Gate Schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The schematic of the JFET sampling gate (see schematic.png ) shows the J1 JFET device used as a switch to sample the instantaneous
1 week ago
010_3phase : Three Phase Schematic
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R The three phase schematic example ( schematic.png ) shows a source of three identical voltage sources that are phase shifted by 120 degrees.