4 weeks ago
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a ring oscillator hierarchical schematic which illustrates the use of the netInherit symbol (see Example13.png). This symbol is from the
4 weeks ago
Minimum Required Versions: Gateway 2.12.8.R, SmartSpice 3.16.11.R This example is a testbench schematic for testing MOS models and devices (see Example14.png). In this example, a LEVEL=1 NMOS device is simulated,
4 weeks ago
Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R Typical Low Noise Amplifier (LNA) designs utilize reasonable gain and a low noise figure to provide stability without oscillation over the useful range
4 weeks ago
Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R RF Example 2 is a mixer design (mixer.png). The three ports of the mixer are the Local Oscillator port (LO), the Radio Frequency
4 weeks ago
Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R The schematic for Example 3 (schematic.png) is a frequency divider design. Since the division factor is 4, the fundamental frequency is set to
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R The Gateway schematic front end can capture digital circuits for netlisting in the verilog format and simulating in the Silvaco SILOS simulator. To
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 2 is an all digital PLL schematic design (all_digital_PLL.png). In the design browser, clickING on the parameters entry displays the parameter names
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 3 is a one bit adder verilog design. The schematic (schematic.png) is shown consisting of gate level primitives and one_bit_adder.v is the
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 4 is a four bit ripple carry counter schematic. The top level of the design (top_level.png) is made from negative edge-triggered T
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 5 is a schematic example of a finite state machine. The example models a vending machine that outputs a newspaper based on
4 weeks ago
Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R The sixth digital example is a drink machine. This example contains structural and RTL/behavioral forms of Verilog. In this example, specify blocks are
4 weeks ago
Minimum Required Version: Expert 4.14.0.R, Guardian 4.14.0.R This example will demonstrate how a Boolean AND function can be used in Guardian DRC to detect Design Rule Check (DRC) errors or