Lateral GaN power devices are close to commercial maturity for switching up to the 650 V class. They still fall short of the material’s theoretical limit for RDS_ON × A against breakdown voltage. Part of that gap is a trade-off between blocking strength and dispersion; part is the limited vertical blocking of GaN on silicon. Two device routes aim to close it:

• Vertical GaN transistors take less wafer area than lateral HFETs, which brings RDS_ON × A down tenfold, to 1.0 mΩ·cm². Strain-free homoepitaxy also allows thick drift layers with low background doping, for blocking above 1 kV.
• Lateral HFETs on an unintentionally doped AlN buffer confine the GaN channel with the large conduction band offset at the buffer interface. The result is stronger blocking and less dispersion.

FBH develops both with physics-based simulation, and Dr. Bahat-Treidel shows where Silvaco tools do the work:

• FBH simulates the conductance of GaN fin MISFETs, checks it against measurement and predicts how it shifts with geometry and epitaxial layers.
• For vertical devices, avalanche models shape the edge terminations, and the results go up against experiment and theory.
• In the AlN/GaN lateral HFET, simulated trapping and de-trapping, with an avalanche model fitted to the epitaxial stack, explains its unusual dynamic on-resistance.