4.25 Gbps SerDes
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Multi-standard SerDes IP: 1.0 to 4.25 Gbps
Four channels of silicon-proven multi-standard SerDes IP from Mixel, a Silvaco company, for SoC teams running PCI Express, SATA, XAUI or backplane links off one block.
Multi-standard SerDes IP, part by part
Start with the process. Everything else matters only if the node fits yours.
| SPECIFICATION | VALUE |
|---|---|
| Part | MXL4254A |
| Silicon-proven on | 130 nm at TSMC and Chartered |
| Channels | Four per quad; quads combine for more lanes |
| Data rate | 1.0 to 4.25 Gbps per channel |
| Supply | 1.2 V, CMOS |
| Transmitter | Programmable output swing and pre-emphasis |
| Receiver | Programmable post-equalization |
| Clocking | Programmable frequency multiplication factor |
| Termination | Programmable, integrated in transmitter and receiver |
| Loopback | Local and remote serial |
| External components | Minimal |
| Standards | PCI Express, SATA, RapidIO, XAUI (10 Gigabit Ethernet), Fibre Channel, SONET, SFI-5, SPI-5, router backplanes |
| Power | Low power dissipation |
Applications
PCI Express and RapidIO
Chip-to-chip and processor-to-peripheral links
SATA and Fibre Channel
Drives, and the networks that connect storage
10 Gigabit Ethernet through XAUI
The link between a 10G MAC and its PHY
SONET, SFI-5 and SPI-5
Line-side and framer links in optical and telecom gear
Router backplanes
Board-to-board links across a chassis
Proven in silicon, characterized in full
130 nm
silicon-proven at TSMC and Chartered
4 channels
per quad, and quads combine
1.0 to 4.25 Gbps
per channel, programmable
Full characterization
data set available for review
Product page · mixel.com
4.25 Gbps Multi-Standard SerDes
Check the full feature list and every compatible standard before you shortlist.
Need it on another node?
Mixel built this design to port between processes, and its channel configuration flexes too. Tell an IP specialist your foundry, node and target rate, and settle licensing on the same call.
Questions about the 4.25 Gbps SerDes
What is a multi-standard SerDes?
A multi-standard SerDes serializes and deserializes data for more than one serial protocol from a single block, so one licensed core can serve several link types on your chip. Mixel's multi-standard SerDes IP gives you four channels covering eight serial standards, PCI Express and SATA among them, plus router backplanes.
What data rates are supported?
Each channel runs anywhere from 1.0 to 4.25 Gbps. Transmit pre-emphasis, output swing, receive post-equalization, termination and the clock multiplication factor are all programmable, which is how one design covers the rates different standards call for. If you need a specific rate on a specific channel, an IP specialist can confirm the setup.
Which standards does it cover?
PCI Express, SATA, RapidIO, 10 Gigabit Ethernet through XAUI, Fibre Channel, SONET, SFI-5, SPI-5 and router backplane links. Targeting a particular version or rate of one of these? Check it with an IP specialist before you plan the rest of the link around it.
Which foundries and nodes are available?
Silicon results exist for 130 nm processes at TSMC and Chartered. Because the design ports, another foundry or node is an open question rather than a dead end. Tell an IP specialist which process you're targeting and ask what's available on it today.
How does it differ from a MIPI PHY?
MIPI PHYs such as D-PHY, C-PHY and M-PHY carry camera, display and storage traffic inside a device, to MIPI Alliance specifications. This SerDes handles general-purpose serial links between chips and boards: PCI Express, SATA, XAUI, backplanes. Silvaco offers both through Mixel, so you can source them from one vendor.
What applications is it used in?
Mostly storage, networking and communications chips. Think drive and storage-network links, 10 Gigabit Ethernet, SONET line cards and their framer interfaces, processor interconnect and router backplanes. And when one quad doesn't give you enough lanes, you combine several quads to reach the channel count you need.