D-PHY LVDS Combo RX
D-PHY LVDS combo receiver IP
Mixel’s D-PHY LVDS combo receiver IP gives your SoC a single input PHY that takes MIPI D-PHY over four lanes or LVDS over four channels, so you don’t redesign the input when the source changes.
Why one receiver for LVDS and D-PHY
The receive side is a different problem from the transmit side.
What it is
A MIPI D-PHY receiver and LVDS deserializers in one PHY, compatible with the TIA/EIA-644 LVDS standard. It is source-synchronous and configured as a MIPI slave, with one clock lane and four data lanes, in high-speed and low-power modes.
The receive side
A transmitter chooses its standard; a receiver has to accept whatever arrives. A combo receiver lets one SoC design take an LVDS source or a MIPI D-PHY source, so the chip does not change with each partner at the other end of the link.
One part, a camera receiver
The receiver listed today is a CSI-2 part, MIPI’s camera interface, in TSMC 28HPC+. For the sending end, see the D-PHY LVDS Combo TX; for LVDS alone, the standalone LVDS parts.
D-PHY LVDS combo receiver IP by foundry
If the part isn’t on your foundry and process, nothing else on the datasheet matters.
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| GlobalFoundries | LVDS/D-PHY DSI TX+ combo in GF 22FDX+ | Supports MIPI D-PHY and LVDS, 4CH/4L, 1039.5Mbps/2.5Gbps, full-speed internal loopback testability | ||
| TSMC | LVDS/D-PHY CSI-2 RX Combo in TSMC 28HPC+ | Supports MIPI D-PHY and LVDS, 4CH/4L, 600Mbps/1.5Gbps | ||
| Tower | LVDS/D-PHY CSI-2 TX Combo in Tower 65BSB | Supports MIPI D-PHY and LVDS, 3CH/2L, 600Mbps/1.2Gbps |
CH is an LVDS channel and L a D-PHY lane; the first rate is per LVDS channel, the second per D-PHY lane. Part 20X285 comes in commercial and industrial grades. If you’re building the transmitting end, the D-PHY LVDS Combo TX page covers it. For another foundry or node, talk to an IP specialist.
Applications
Where a dual-standard input fits.
Inputs that must take either standard
An SoC input that meets LVDS in one product and D-PHY in the next.
Automotive camera and display inputs
The part isn’t listed in an automotive grade, so settle qualification with an IP specialist before you commit.
Industrial camera and panel inputs
LVDS or D-PHY from the sensor or panel side, on one PHY sold in an industrial grade.
Proof and resources
Before you shortlist, check the part against the catalog and the announcement.
TSMC 28HPC+
foundry and process for the combo receiver
TIA/EIA-644
the LVDS standard it’s compatible with
4CH · 600 Mbps
LVDS channels, rate per channel
4L · 1.5 Gbps
D-PHY lanes, rate per lane
Customer · Mixel D-PHY IP
November 2025
indie
indie’s automotive radar processors carry Mixel’s ASIL-B MIPI D-PHY CSI-2 TX and RX IP. That’s D-PHY IP rather than this combo, from the same Mixel team.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability. We are looking forward to our continued collaboration.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
Summer 2026
PRO IP product selection guide
Find the combo receiver by foundry, process and part number, listed alongside both combo transmitters and Silvaco’s wider PRO IP range.
Press release
March 2026
Mixel MIPI PHY IP available as Silvaco PRO IP
Both directions of the D-PHY/LVDS combo are in the announcement, transmit and receive, each running D-PHY or TIA/EIA-644 LVDS.
Bring your node and your source
Tell an IP specialist which foundry and process you’re on and what’s driving the input. You’ll get the datasheet and licensing terms for your node. Your license includes the first year of support.
Questions about D-PHY LVDS combo receiver IP
What is a D-PHY LVDS combo receiver?
It’s one receive PHY with two modes: MIPI D-PHY, or LVDS to the TIA/EIA-644 standard. Mixel’s receiver runs as the MIPI slave on a source-synchronous link, using a clock lane plus four data lanes, in high-speed or low-power operation. The part on offer is a CSI-2 receiver on TSMC 28HPC+.
When is a combo receiver needed?
When your chip has to accept an input someone else chose. If one customer’s source is LVDS and another’s is MIPI D-PHY, a combo receiver lets a single SoC design serve both. The alternative is two input PHYs on the die, and two integrations to close before tape-out.
Which foundries and nodes are available?
TSMC 28HPC+, part number 20X285, sold in commercial and industrial grades. That’s the only combo receiver in the catalog at the moment. If you’re on a different foundry or process, an IP specialist can tell you where that stands for your node and tape-out date.
What data rates are supported?
Up to 1.5 Gbps per lane across four MIPI D-PHY lanes, or up to 600 Mbps per channel across four LVDS channels. It’s a CSI-2 part, built for MIPI’s camera serial interface. If you need D-PHY alone at higher rates, the standalone MIPI D-PHY parts reach 4.5 Gbps per lane.
How does this pair with the combo transmitter?
They’re the two ends of one link type, and you license each on its own. Silvaco’s two combo transmitters are a DSI TX+ on GlobalFoundries 22FDX+ and a CSI-2 TX on Tower 65BSB. Neither shares a foundry with this receiver, so you pick each end for its own chip. Ask an IP specialist for a briefing on pairing them.
How does this differ from a separate LVDS receiver?
A standalone LVDS receiver takes LVDS and nothing else. Silvaco’s four-channel LVDS RX on TSMC 40LP handles 1000 Mbps per channel. The combo lists 600 Mbps per LVDS channel and adds a second mode, MIPI D-PHY at 1.5 Gbps per lane, on TSMC 28HPC+. Choose it when you can’t predict the source.
Related
D-PHY LVDS Combo TX
Transmit-side combo parts, on GlobalFoundries 22FDX+ and Tower 65BSB.
LVDS
Serializers and deserializers for LVDS-only links.
MIPI D-PHY
Standalone D-PHY transmitters and receivers, up to 4.5 Gbps per lane.
Multi-Standard
Combo PHYs for C-PHY/D-PHY and D-PHY/LVDS, plus the 4.25 Gbps SerDes.